mirror of https://github.com/acidanthera/audk.git
OvmfPkg/VmgExitLib: Check for an explicit DR7 cached value
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3108 Check the DR7 cached indicator against a specific value. This makes it harder for a hypervisor to just write random data into that field in an attempt to use an invalid DR7 value. Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ard Biesheuvel <ard.biesheuvel@arm.com> Cc: Brijesh Singh <brijesh.singh@amd.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Message-Id: <65157c1155a9c058c43678400dfc0b486e327a3e.1610045305.git.thomas.lendacky@amd.com>
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@ -128,10 +128,13 @@ UINT64
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//
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// Per-CPU data mapping structure
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// Use UINT32 for cached indicators and compare to a specific value
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// so that the hypervisor can't indicate a value is cached by just
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// writing random data to that area.
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//
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typedef struct {
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BOOLEAN Dr7Cached;
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UINT64 Dr7;
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UINT32 Dr7Cached;
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UINT64 Dr7;
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} SEV_ES_PER_CPU_DATA;
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@ -1489,7 +1492,7 @@ Dr7WriteExit (
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}
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SevEsData->Dr7 = *Register;
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SevEsData->Dr7Cached = TRUE;
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SevEsData->Dr7Cached = 1;
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return 0;
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}
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@ -1533,7 +1536,7 @@ Dr7ReadExit (
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// If there is a cached valued for DR7, return that. Otherwise return the
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// DR7 standard reset value of 0x400 (no debug breakpoints set).
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//
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*Register = (SevEsData->Dr7Cached) ? SevEsData->Dr7 : 0x400;
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*Register = (SevEsData->Dr7Cached == 1) ? SevEsData->Dr7 : 0x400;
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return 0;
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}
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