mirror of https://github.com/acidanthera/audk.git
Clean up hard-coded offsets and other utter bogosity in Thunk16.S
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15028 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
David Woodhouse
lgao4
parent
efd6b412c6
commit
321c89c208
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@ -24,6 +24,28 @@
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ASM_GLOBAL ASM_PFX(m16Start), ASM_PFX(m16Size), ASM_PFX(mThunk16Attr), ASM_PFX(m16Gdt), ASM_PFX(m16GdtrBase), ASM_PFX(mTransition)
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ASM_GLOBAL ASM_PFX(m16Start), ASM_PFX(m16Size), ASM_PFX(mThunk16Attr), ASM_PFX(m16Gdt), ASM_PFX(m16GdtrBase), ASM_PFX(mTransition)
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ASM_GLOBAL ASM_PFX(InternalAsmThunk16)
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ASM_GLOBAL ASM_PFX(InternalAsmThunk16)
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# define the structure of IA32_REGS
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.set _EDI, 0 #size 4
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.set _ESI, 4 #size 4
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.set _EBP, 8 #size 4
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.set _ESP, 12 #size 4
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.set _EBX, 16 #size 4
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.set _EDX, 20 #size 4
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.set _ECX, 24 #size 4
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.set _EAX, 28 #size 4
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.set _DS, 32 #size 2
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.set _ES, 34 #size 2
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.set _FS, 36 #size 2
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.set _GS, 38 #size 2
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.set _EFLAGS, 40 #size 4
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.set _EIP, 44 #size 4
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.set _CS, 48 #size 2
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.set _SS, 50 #size 2
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.set IA32_REGS_SIZE, 52
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.text
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.code16
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ASM_PFX(m16Start):
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ASM_PFX(m16Start):
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SavedGdt: .space 6
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SavedGdt: .space 6
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@ -31,21 +53,22 @@ SavedGdt: .space 6
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ASM_PFX(BackFromUserCode):
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ASM_PFX(BackFromUserCode):
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push %ss
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push %ss
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push %cs
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push %cs
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.byte 0x66
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call L_Base1 # push eip
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calll L_Base1 # push eip
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L_Base1:
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L_Base1:
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pushfw # pushfd actually
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pushfl
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cli # disable interrupts
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cli # disable interrupts
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push %gs
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push %gs
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push %fs
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push %fs
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push %es
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push %es
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push %ds
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push %ds
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pushaw # pushad actually
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pushal
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.byte 0x66, 0xba # mov edx, imm32
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.byte 0x66, 0xba # mov edx, imm32
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ASM_PFX(ThunkAttr): .space 4
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ASM_PFX(ThunkAttr): .space 4
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testb $THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15, %dl
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testb $THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15, %dl
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jz 1f
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jz 1f
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movl $0x15cd2401, %eax # mov ax, 2401h & int 15h
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movw $0x2401, %ax
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int $0x15
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cli # disable interrupts
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cli # disable interrupts
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jnc 2f
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jnc 2f
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1:
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1:
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@ -55,27 +78,26 @@ ASM_PFX(ThunkAttr): .space 4
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orb $2, %al
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orb $2, %al
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outb %al, $0x92 # deactivate A20M#
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outb %al, $0x92 # deactivate A20M#
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2:
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2:
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xorw %ax, %ax # xor eax, eax
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xorl %eax, %eax
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movl %ss, %eax # mov ax, ss
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movw %ss, %ax
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.byte 0x67, 0x66, 0x8d, 0x6c, 0x24, 0x34, 0x66
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leal IA32_REGS_SIZE(%esp), %ebp
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mov %ebp, 0xffffffd8(%esi)
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mov %ebp, (_ESP - IA32_REGS_SIZE)(%bp)
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mov 0xfffffff8(%esi), %ebx
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mov (_EIP - IA32_REGS_SIZE)(%bp), %bx
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shlw $4, %ax # shl eax, 4
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shll $4, %eax
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addw %ax, %bp # add ebp, eax
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addl %eax, %ebp
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.byte 0x66, 0xb8 # mov eax, imm32
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.byte 0x66, 0xb8 # mov eax, imm32
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SavedCr4: .space 4
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SavedCr4: .space 4
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movl %eax, %cr4
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movl %eax, %cr4
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lgdtw %cs:0xfffffff2(%edi)
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lgdtl %cs:(SavedGdt - L_Base1)(%bx)
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.byte 0x66, 0xb8 # mov eax, imm32
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.byte 0x66, 0xb8 # mov eax, imm32
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SavedCr0: .space 4
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SavedCr0: .space 4
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movl %eax, %cr0
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movl %eax, %cr0
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.byte 0xb8 # mov ax, imm16
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.byte 0xb8 # mov ax, imm16
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SavedSs: .space 2
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SavedSs: .space 2
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movl %eax, %ss
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movl %eax, %ss
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.byte 0x66, 0xbc # mov esp, imm32
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.byte 0x66, 0xbc # mov esp, imm32
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SavedEsp: .space 4
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SavedEsp: .space 4
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.byte 0x66
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lretl # return to protected mode
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lret # return to protected mode
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_EntryPoint: .long ASM_PFX(ToUserCode) - ASM_PFX(m16Start)
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_EntryPoint: .long ASM_PFX(ToUserCode) - ASM_PFX(m16Start)
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.word 0x8
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.word 0x8
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@ -85,37 +107,35 @@ _16Gdtr: .word GdtEnd - _NullSegDesc - 1
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_16GdtrBase: .long _NullSegDesc
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_16GdtrBase: .long _NullSegDesc
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ASM_PFX(ToUserCode):
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ASM_PFX(ToUserCode):
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movl %ss, %edx
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movw %ss, %dx
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movl %ecx, %ss # set new segment selectors
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movw %cx, %ss # set new segment selectors
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movl %ecx, %ds
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movw %cx, %ds
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movl %ecx, %es
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movw %cx, %es
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movl %ecx, %fs
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movw %cx, %fs
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movl %ecx, %gs
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movw %cx, %gs
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movl %eax, %cr0
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movl %eax, %cr0
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movl %ebp, %cr4 # real mode starts at next instruction
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movl %ebp, %cr4 # real mode starts at next instruction
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movl %esi, %ss # set up 16-bit stack segment
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movw %si, %ss # set up 16-bit stack segment
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xchgw %bx, %sp # set up 16-bit stack pointer
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xchgl %ebx, %esp # set up 16-bit stack pointer
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.byte 0x66
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calll L_Base # push eip
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call L_Base # push eip
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L_Base:
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L_Base:
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popw %bp # ebp <- offset L_Base
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popl %ebp # ebp <- offset L_Base
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.byte 0x67; # address size override
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push (IA32_REGS_SIZE + 2)(%esp)
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push 54(%esp)
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lea (L_RealMode - L_Base)(%bp), %ax
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lea 0xc(%esi), %eax
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push %ax
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push %eax
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lret
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lret
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L_RealMode:
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L_RealMode:
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mov %edx, %cs:0xffffffc5(%esi)
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mov %dx, %cs:(SavedSs - L_Base)(%bp)
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mov %bx, %cs:0xffffffcb(%esi)
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mov %ebx, %cs:(SavedEsp - L_Base)(%bp)
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lidtw %cs:0xffffffd7(%esi)
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lidtl %cs:(_16Idtr - L_Base)(%bp)
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popaw # popad actually
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popal
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pop %ds
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pop %ds
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pop %es
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pop %es
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pop %fs
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pop %fs
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pop %gs
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pop %gs
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popfw # popfd
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popfl
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lretw # transfer control to user code
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lretl # transfer control to user code
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_NullSegDesc: .quad 0
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_NullSegDesc: .quad 0
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_16CsDesc:
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_16CsDesc:
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@ -134,6 +154,7 @@ _16DsDesc:
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.byte 0
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.byte 0
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GdtEnd:
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GdtEnd:
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.code32
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#
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#
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# @param RegSet The pointer to a IA32_DWORD_REGS structure
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# @param RegSet The pointer to a IA32_DWORD_REGS structure
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# @param Transition The pointer to the transition code
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# @param Transition The pointer to the transition code
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@ -149,41 +170,41 @@ ASM_PFX(InternalAsmThunk16):
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push %fs
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push %fs
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push %gs
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push %gs
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movl 36(%esp), %esi # esi <- RegSet
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movl 36(%esp), %esi # esi <- RegSet
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movzwl 0x32(%esi), %edx
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movzwl _SS(%esi), %edx
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mov 0xc(%esi), %edi
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mov _ESP(%esi), %edi
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add $0xffffffc8, %edi
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add $(-(IA32_REGS_SIZE + 4)), %edi
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movl %edi, %ebx # ebx <- stack offset
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movl %edi, %ebx # ebx <- stack offset
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imul $0x10, %edx, %eax
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imul $0x10, %edx, %eax
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push $0xd
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push $(IA32_REGS_SIZE / 4)
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addl %eax, %edi # edi <- linear address of 16-bit stack
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addl %eax, %edi # edi <- linear address of 16-bit stack
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pop %ecx
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pop %ecx
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rep
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rep
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movsl # copy RegSet
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movsl # copy RegSet
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movl 40(%esp), %eax # eax <- address of transition code
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movl 40(%esp), %eax # eax <- address of transition code
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movl %edx, %esi # esi <- 16-bit stack segment
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movl %edx, %esi # esi <- 16-bit stack segment
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lea 0x61(%eax), %edx
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lea (SavedCr0 - ASM_PFX(m16Start))(%eax), %edx
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movl %eax, %ecx
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movl %eax, %ecx
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andl $0xf, %ecx
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andl $0xf, %ecx
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shll $12, %eax
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shll $12, %eax
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lea 0x6(%ecx), %ecx
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lea (ASM_PFX(BackFromUserCode) - ASM_PFX(m16Start))(%ecx), %ecx
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movw %cx, %ax
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movw %cx, %ax
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stosl # [edi] <- return address of user code
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stosl # [edi] <- return address of user code
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sgdtl 0xffffff9f(%edx)
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sgdtl (SavedGdt - SavedCr0)(%edx)
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sidtl 0x24(%esp)
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sidtl 0x24(%esp)
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movl %cr0, %eax
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movl %cr0, %eax
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movl %eax, (%edx) # save CR0 in SavedCr0
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movl %eax, (%edx) # save CR0 in SavedCr0
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andl $0x7ffffffe, %eax # clear PE, PG bits
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andl $0x7ffffffe, %eax # clear PE, PG bits
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movl %cr4, %ebp
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movl %cr4, %ebp
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mov %ebp, 0xfffffff1(%edx)
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mov %ebp, (SavedCr4 - SavedCr0)(%edx)
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andl $0xffffffcf, %ebp # clear PAE, PSE bits
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andl $0xffffffcf, %ebp # clear PAE, PSE bits
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pushl $0x10
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pushl $0x10
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pop %ecx # ecx <- selector for data segments
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pop %ecx # ecx <- selector for data segments
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lgdtl 0x20(%edx)
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lgdtl (_16Gdtr - SavedCr0)(%edx)
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pushfl
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pushfl
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lcall *0x14(%edx)
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lcall *(_EntryPoint - SavedCr0)(%edx)
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popfl
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popfl
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lidtl 0x24(%esp)
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lidtl 0x24(%esp)
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lea 0xffffffcc(%ebp), %eax
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lea -IA32_REGS_SIZE(%ebp), %eax
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pop %gs
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pop %gs
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pop %fs
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pop %fs
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pop %es
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pop %es
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