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Make EOL consistent

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git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9116 6f19259b-4bc3-4df7-8a09-765794883524
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mdkinney 2009-08-18 22:19:04 +00:00
parent 4b5f371b7d
commit 32304af268
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486
MdePkg/Library/BaseCacheMaintenanceLib/ArmCache.c
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@ -1,247 +1,247 @@
/** @file /** @file
Cache Maintenance Functions. These functions vary by ARM architecture so the MdePkg Cache Maintenance Functions. These functions vary by ARM architecture so the MdePkg
versions are null functions used to make sure things will compile. versions are null functions used to make sure things will compile.
Copyright (c) 2006 - 2009, Intel Corporation<BR> Copyright (c) 2006 - 2009, Intel Corporation<BR>
Portions copyright (c) 2008-2009 Apple Inc.<BR> Portions copyright (c) 2008-2009 Apple Inc.<BR>
All rights reserved. This program and the accompanying materials All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/ **/
// //
// Include common header file for this module. // Include common header file for this module.
// //
#include <Base.h> #include <Base.h>
#include <Library/DebugLib.h> #include <Library/DebugLib.h>
/** /**
Invalidates the entire instruction cache in cache coherency domain of the Invalidates the entire instruction cache in cache coherency domain of the
calling CPU. calling CPU.
Invalidates the entire instruction cache in cache coherency domain of the Invalidates the entire instruction cache in cache coherency domain of the
calling CPU. calling CPU.
**/ **/
VOID VOID
EFIAPI EFIAPI
InvalidateInstructionCache ( InvalidateInstructionCache (
VOID VOID
) )
{ {
ASSERT(FALSE); ASSERT(FALSE);
} }
/** /**
Invalidates a range of instruction cache lines in the cache coherency domain Invalidates a range of instruction cache lines in the cache coherency domain
of the calling CPU. of the calling CPU.
Invalidates the instruction cache lines specified by Address and Length. If Invalidates the instruction cache lines specified by Address and Length. If
Address is not aligned on a cache line boundary, then entire instruction Address is not aligned on a cache line boundary, then entire instruction
cache line containing Address is invalidated. If Address + Length is not cache line containing Address is invalidated. If Address + Length is not
aligned on a cache line boundary, then the entire instruction cache line aligned on a cache line boundary, then the entire instruction cache line
containing Address + Length -1 is invalidated. This function may choose to containing Address + Length -1 is invalidated. This function may choose to
invalidate the entire instruction cache if that is more efficient than invalidate the entire instruction cache if that is more efficient than
invalidating the specified range. If Length is 0, the no instruction cache invalidating the specified range. If Length is 0, the no instruction cache
lines are invalidated. Address is returned. lines are invalidated. Address is returned.
If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
@param Address The base address of the instruction cache lines to @param Address The base address of the instruction cache lines to
invalidate. If the CPU is in a physical addressing mode, then invalidate. If the CPU is in a physical addressing mode, then
Address is a physical address. If the CPU is in a virtual Address is a physical address. If the CPU is in a virtual
addressing mode, then Address is a virtual address. addressing mode, then Address is a virtual address.
@param Length The number of bytes to invalidate from the instruction cache. @param Length The number of bytes to invalidate from the instruction cache.
@return Address @return Address
**/ **/
VOID * VOID *
EFIAPI EFIAPI
InvalidateInstructionCacheRange ( InvalidateInstructionCacheRange (
IN VOID *Address, IN VOID *Address,
IN UINTN Length IN UINTN Length
) )
{ {
ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1); ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
ASSERT(FALSE); ASSERT(FALSE);
return Address; return Address;
} }
/** /**
Writes Back and Invalidates the entire data cache in cache coherency domain Writes Back and Invalidates the entire data cache in cache coherency domain
of the calling CPU. of the calling CPU.
Writes Back and Invalidates the entire data cache in cache coherency domain Writes Back and Invalidates the entire data cache in cache coherency domain
of the calling CPU. This function guarantees that all dirty cache lines are of the calling CPU. This function guarantees that all dirty cache lines are
written back to system memory, and also invalidates all the data cache lines written back to system memory, and also invalidates all the data cache lines
in the cache coherency domain of the calling CPU. in the cache coherency domain of the calling CPU.
**/ **/
VOID VOID
EFIAPI EFIAPI
WriteBackInvalidateDataCache ( WriteBackInvalidateDataCache (
VOID VOID
) )
{ {
ASSERT(FALSE); ASSERT(FALSE);
} }
/** /**
Writes Back and Invalidates a range of data cache lines in the cache Writes Back and Invalidates a range of data cache lines in the cache
coherency domain of the calling CPU. coherency domain of the calling CPU.
Writes Back and Invalidate the data cache lines specified by Address and Writes Back and Invalidate the data cache lines specified by Address and
Length. If Address is not aligned on a cache line boundary, then entire data Length. If Address is not aligned on a cache line boundary, then entire data
cache line containing Address is written back and invalidated. If Address + cache line containing Address is written back and invalidated. If Address +
Length is not aligned on a cache line boundary, then the entire data cache Length is not aligned on a cache line boundary, then the entire data cache
line containing Address + Length -1 is written back and invalidated. This line containing Address + Length -1 is written back and invalidated. This
function may choose to write back and invalidate the entire data cache if function may choose to write back and invalidate the entire data cache if
that is more efficient than writing back and invalidating the specified that is more efficient than writing back and invalidating the specified
range. If Length is 0, the no data cache lines are written back and range. If Length is 0, the no data cache lines are written back and
invalidated. Address is returned. invalidated. Address is returned.
If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
@param Address The base address of the data cache lines to write back and @param Address The base address of the data cache lines to write back and
invalidate. If the CPU is in a physical addressing mode, then invalidate. If the CPU is in a physical addressing mode, then
Address is a physical address. If the CPU is in a virtual Address is a physical address. If the CPU is in a virtual
addressing mode, then Address is a virtual address. addressing mode, then Address is a virtual address.
@param Length The number of bytes to write back and invalidate from the @param Length The number of bytes to write back and invalidate from the
data cache. data cache.
@return Address @return Address
**/ **/
VOID * VOID *
EFIAPI EFIAPI
WriteBackInvalidateDataCacheRange ( WriteBackInvalidateDataCacheRange (
IN VOID *Address, IN VOID *Address,
IN UINTN Length IN UINTN Length
) )
{ {
ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1); ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
ASSERT(FALSE); ASSERT(FALSE);
return Address; return Address;
} }
/** /**
Writes Back the entire data cache in cache coherency domain of the calling Writes Back the entire data cache in cache coherency domain of the calling
CPU. CPU.
Writes Back the entire data cache in cache coherency domain of the calling Writes Back the entire data cache in cache coherency domain of the calling
CPU. This function guarantees that all dirty cache lines are written back to CPU. This function guarantees that all dirty cache lines are written back to
system memory. This function may also invalidate all the data cache lines in system memory. This function may also invalidate all the data cache lines in
the cache coherency domain of the calling CPU. the cache coherency domain of the calling CPU.
**/ **/
VOID VOID
EFIAPI EFIAPI
WriteBackDataCache ( WriteBackDataCache (
VOID VOID
) )
{ {
ASSERT(FALSE); ASSERT(FALSE);
} }
/** /**
Writes Back a range of data cache lines in the cache coherency domain of the Writes Back a range of data cache lines in the cache coherency domain of the
calling CPU. calling CPU.
Writes Back the data cache lines specified by Address and Length. If Address Writes Back the data cache lines specified by Address and Length. If Address
is not aligned on a cache line boundary, then entire data cache line is not aligned on a cache line boundary, then entire data cache line
containing Address is written back. If Address + Length is not aligned on a containing Address is written back. If Address + Length is not aligned on a
cache line boundary, then the entire data cache line containing Address + cache line boundary, then the entire data cache line containing Address +
Length -1 is written back. This function may choose to write back the entire Length -1 is written back. This function may choose to write back the entire
data cache if that is more efficient than writing back the specified range. data cache if that is more efficient than writing back the specified range.
If Length is 0, the no data cache lines are written back. This function may If Length is 0, the no data cache lines are written back. This function may
also invalidate all the data cache lines in the specified range of the cache also invalidate all the data cache lines in the specified range of the cache
coherency domain of the calling CPU. Address is returned. coherency domain of the calling CPU. Address is returned.
If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
@param Address The base address of the data cache lines to write back. If @param Address The base address of the data cache lines to write back. If
the CPU is in a physical addressing mode, then Address is a the CPU is in a physical addressing mode, then Address is a
physical address. If the CPU is in a virtual addressing physical address. If the CPU is in a virtual addressing
mode, then Address is a virtual address. mode, then Address is a virtual address.
@param Length The number of bytes to write back from the data cache. @param Length The number of bytes to write back from the data cache.
@return Address @return Address
**/ **/
VOID * VOID *
EFIAPI EFIAPI
WriteBackDataCacheRange ( WriteBackDataCacheRange (
IN VOID *Address, IN VOID *Address,
IN UINTN Length IN UINTN Length
) )
{ {
ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1); ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
ASSERT(FALSE); ASSERT(FALSE);
return Address; return Address;
} }
/** /**
Invalidates the entire data cache in cache coherency domain of the calling Invalidates the entire data cache in cache coherency domain of the calling
CPU. CPU.
Invalidates the entire data cache in cache coherency domain of the calling Invalidates the entire data cache in cache coherency domain of the calling
CPU. This function must be used with care because dirty cache lines are not CPU. This function must be used with care because dirty cache lines are not
written back to system memory. It is typically used for cache diagnostics. If written back to system memory. It is typically used for cache diagnostics. If
the CPU does not support invalidation of the entire data cache, then a write the CPU does not support invalidation of the entire data cache, then a write
back and invalidate operation should be performed on the entire data cache. back and invalidate operation should be performed on the entire data cache.
**/ **/
VOID VOID
EFIAPI EFIAPI
InvalidateDataCache ( InvalidateDataCache (
VOID VOID
) )
{ {
ASSERT(FALSE); ASSERT(FALSE);
} }
/** /**
Invalidates a range of data cache lines in the cache coherency domain of the Invalidates a range of data cache lines in the cache coherency domain of the
calling CPU. calling CPU.
Invalidates the data cache lines specified by Address and Length. If Address Invalidates the data cache lines specified by Address and Length. If Address
is not aligned on a cache line boundary, then entire data cache line is not aligned on a cache line boundary, then entire data cache line
containing Address is invalidated. If Address + Length is not aligned on a containing Address is invalidated. If Address + Length is not aligned on a
cache line boundary, then the entire data cache line containing Address + cache line boundary, then the entire data cache line containing Address +
Length -1 is invalidated. This function must never invalidate any cache lines Length -1 is invalidated. This function must never invalidate any cache lines
outside the specified range. If Length is 0, the no data cache lines are outside the specified range. If Length is 0, the no data cache lines are
invalidated. Address is returned. This function must be used with care invalidated. Address is returned. This function must be used with care
because dirty cache lines are not written back to system memory. It is because dirty cache lines are not written back to system memory. It is
typically used for cache diagnostics. If the CPU does not support typically used for cache diagnostics. If the CPU does not support
invalidation of a data cache range, then a write back and invalidate invalidation of a data cache range, then a write back and invalidate
operation should be performed on the data cache range. operation should be performed on the data cache range.
If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
@param Address The base address of the data cache lines to invalidate. If @param Address The base address of the data cache lines to invalidate. If
the CPU is in a physical addressing mode, then Address is a the CPU is in a physical addressing mode, then Address is a
physical address. If the CPU is in a virtual addressing mode, physical address. If the CPU is in a virtual addressing mode,
then Address is a virtual address. then Address is a virtual address.
@param Length The number of bytes to invalidate from the data cache. @param Length The number of bytes to invalidate from the data cache.
@return Address @return Address
**/ **/
VOID * VOID *
EFIAPI EFIAPI
InvalidateDataCacheRange ( InvalidateDataCacheRange (
IN VOID *Address, IN VOID *Address,
IN UINTN Length IN UINTN Length
) )
{ {
ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1); ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
ASSERT(FALSE); ASSERT(FALSE);
return Address; return Address;
} }