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IntelSiliconPkg\Include\IndustryStandard: Update IGD_OPREGION_MBOX3 Structure 

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1454
Based on latest IGD OpRegion Spec, IGD_OPREGION_MBOX3 needs to be updated with two new members : Physical Address of Raw VBT Data (RVDA) and Size of Raw VBT Data (RVDS)

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Digant H Solanki <digant.h.solanki@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
This commit is contained in:
Solanki, Digant H 2019-01-31 16:01:09 +08:00 committed by Ruiyu Ni
parent 9747329114
commit 34c5a69a2b
1 changed files with 4 additions and 4 deletions
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8
IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion.h
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@ -4,9 +4,7 @@
https://01.org/sites/default/files/documentation/skl_opregion_rev0p5.pdf
@note Fixed bug in the spec Mailbox3 - RM31 size from 0x45(69) to 0x46(70)
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -118,7 +116,9 @@ typedef struct {
UINT64 FDSS; ///< Offset 0x3AA DSS Buffer address allocated for IFFS feature
UINT32 FDSP; ///< Offset 0x3B2 Size of DSS buffer
UINT32 STAT; ///< Offset 0x3B6 State Indicator
UINT8 RM31[0x46]; ///< Offset 0x3BA - 0x3FF Reserved Must be zero. Bug in spec 0x45(69)
UINT64 RVDA; ///< Offset 0x3BA Physical address of Raw VBT data. Added from Spec Version 0.90 to support VBT greater than 6KB.
UINT32 RVDS; ///< Offset 0x3C2 Size of Raw VBT data. Added from Spec Version 0.90 to support VBT greater than 6KB.
UINT8 RM32[0x3A]; ///< Offset 0x3C6 - 0x3FF Reserved Must be zero.
} IGD_OPREGION_MBOX3;
///