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ArmPkg: Remove RVCT support

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RVCT is obsolete and no longer used.
Remove support for it.

Signed-off-by: Rebecca Cran <quic_rcran@quicinc.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
This commit is contained in:
Rebecca Cran 2022-05-04 02:48:11 +08:00 committed by mergify[bot]
parent ef01d63ef3
commit 35d9b7ea2d
27 changed files with 0 additions and 1552 deletions
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1
ArmPkg/Drivers/ArmGic/ArmGicLib.inf
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@ -22,7 +22,6 @@
[Sources.ARM]
GicV3/Arm/ArmGicV3.S | GCC
GicV3/Arm/ArmGicV3.asm | RVCT
[Sources.AARCH64]
GicV3/AArch64/ArmGicV3.S

82
ArmPkg/Drivers/ArmGic/GicV3/Arm/ArmGicV3.asm
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@ -1,82 +0,0 @@
//
// Copyright (c) 2014, ARM Limited. All rights reserved.
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
//
// For the moment we assume this will run in SVC mode on ARMv7
INCLUDE AsmMacroExport.inc
//UINT32
//EFIAPI
//ArmGicGetControlSystemRegisterEnable (
// VOID
// );
RVCT_ASM_EXPORT ArmGicV3GetControlSystemRegisterEnable
mrc p15, 0, r0, c12, c12, 5 // ICC_SRE
bx lr
//VOID
//EFIAPI
//ArmGicSetControlSystemRegisterEnable (
// IN UINT32 ControlSystemRegisterEnable
// );
RVCT_ASM_EXPORT ArmGicV3SetControlSystemRegisterEnable
mcr p15, 0, r0, c12, c12, 5 // ICC_SRE
isb
bx lr
//VOID
//ArmGicV3EnableInterruptInterface (
// VOID
// );
RVCT_ASM_EXPORT ArmGicV3EnableInterruptInterface
mov r0, #1
mcr p15, 0, r0, c12, c12, 7 // ICC_IGRPEN1
bx lr
//VOID
//ArmGicV3DisableInterruptInterface (
// VOID
// );
RVCT_ASM_EXPORT ArmGicV3DisableInterruptInterface
mov r0, #0
mcr p15, 0, r0, c12, c12, 7 // ICC_IGRPEN1
bx lr
//VOID
//ArmGicV3EndOfInterrupt (
// IN UINTN InterruptId
// );
RVCT_ASM_EXPORT ArmGicV3EndOfInterrupt
mcr p15, 0, r0, c12, c12, 1 //ICC_EOIR1
bx lr
//UINTN
//ArmGicV3AcknowledgeInterrupt (
// VOID
// );
RVCT_ASM_EXPORT ArmGicV3AcknowledgeInterrupt
mrc p15, 0, r0, c12, c12, 0 //ICC_IAR1
bx lr
//VOID
//ArmGicV3SetPriorityMask (
// IN UINTN Priority
// );
RVCT_ASM_EXPORT ArmGicV3SetPriorityMask
mcr p15, 0, r0, c4, c6, 0 //ICC_PMR
bx lr
//VOID
//ArmGicV3SetBinaryPointer (
// IN UINTN BinaryPoint
// );
RVCT_ASM_EXPORT ArmGicV3SetBinaryPointer
mcr p15, 0, r0, c12, c12, 3 //ICC_BPR1
bx lr
END

23
ArmPkg/Include/AsmMacroExport.inc
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@ -1,23 +0,0 @@
;%HEADER%
;/** @file
; Macros to centralize the EXPORT, AREA, and definition of an assembly
; function. The AREA prefix is required to put the function in its own
; section so that removal of unused functions in the final link is performed.
; This provides equivalent functionality to the compiler's --split-sections
; option.
;
; Copyright (c) 2015 HP Development Company, L.P.
;
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
;**/
MACRO
RVCT_ASM_EXPORT $func
EXPORT $func
AREA s_$func, CODE, READONLY
$func
MEND
END

296
ArmPkg/Library/ArmExceptionLib/Arm/ExceptionSupport.asm
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@ -1,296 +0,0 @@
//------------------------------------------------------------------------------
//
// Use ARMv6 instruction to operate on a single stack
//
// Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
// Copyright (c) 2014, ARM Limited. All rights reserved.<BR>
// Copyright (c) 2016 HP Development Company, L.P.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
//------------------------------------------------------------------------------
#include <Library/PcdLib.h>
/*
This is the stack constructed by the exception handler (low address to high address)
# R0 - IFAR is EFI_SYSTEM_CONTEXT for ARM
Reg Offset
=== ======
R0 0x00 # stmfd SP!,{R0-R12}
R1 0x04
R2 0x08
R3 0x0c
R4 0x10
R5 0x14
R6 0x18
R7 0x1c
R8 0x20
R9 0x24
R10 0x28
R11 0x2c
R12 0x30
SP 0x34 # reserved via subtraction 0x20 (32) from SP
LR 0x38
PC 0x3c
CPSR 0x40
DFSR 0x44
DFAR 0x48
IFSR 0x4c
IFAR 0x50
LR 0x54 # SVC Link register (we need to restore it)
LR 0x58 # pushed by srsfd
CPSR 0x5c
*/
EXPORT ExceptionHandlersStart
EXPORT ExceptionHandlersEnd
EXPORT CommonExceptionEntry
EXPORT AsmCommonExceptionEntry
IMPORT CommonCExceptionHandler
PRESERVE8
AREA DxeExceptionHandlers, CODE, READONLY, CODEALIGN, ALIGN=5
//
// This code gets copied to the ARM vector table
// ExceptionHandlersStart - ExceptionHandlersEnd gets copied
//
ExceptionHandlersStart
Reset
b ResetEntry
UndefinedInstruction
b UndefinedInstructionEntry
SoftwareInterrupt
b SoftwareInterruptEntry
PrefetchAbort
b PrefetchAbortEntry
DataAbort
b DataAbortEntry
ReservedException
b ReservedExceptionEntry
Irq
b IrqEntry
Fiq
b FiqEntry
ResetEntry
srsfd #0x13! ; Store return state on SVC stack
; We are already in SVC mode
stmfd SP!,{LR} ; Store the link register for the current mode
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} ; Store the register state
mov R0,#0 ; ExceptionType
ldr R1,CommonExceptionEntry
bx R1
UndefinedInstructionEntry
sub LR, LR, #4 ; Only -2 for Thumb, adjust in CommonExceptionEntry
srsfd #0x13! ; Store return state on SVC stack
cps #0x13 ; Switch to SVC for common stack
stmfd SP!,{LR} ; Store the link register for the current mode
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} ; Store the register state
mov R0,#1 ; ExceptionType
ldr R1,CommonExceptionEntry;
bx R1
SoftwareInterruptEntry
srsfd #0x13! ; Store return state on SVC stack
; We are already in SVC mode
stmfd SP!,{LR} ; Store the link register for the current mode
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} ; Store the register state
mov R0,#2 ; ExceptionType
ldr R1,CommonExceptionEntry
bx R1
PrefetchAbortEntry
sub LR,LR,#4
srsfd #0x13! ; Store return state on SVC stack
cps #0x13 ; Switch to SVC for common stack
stmfd SP!,{LR} ; Store the link register for the current mode
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} ; Store the register state
mov R0,#3 ; ExceptionType
ldr R1,CommonExceptionEntry
bx R1
DataAbortEntry
sub LR,LR,#8
srsfd #0x13! ; Store return state on SVC stack
cps #0x13 ; Switch to SVC for common stack
stmfd SP!,{LR} ; Store the link register for the current mode
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} ; Store the register state
mov R0,#4 ; ExceptionType
ldr R1,CommonExceptionEntry
bx R1
ReservedExceptionEntry
srsfd #0x13! ; Store return state on SVC stack
cps #0x13 ; Switch to SVC for common stack
stmfd SP!,{LR} ; Store the link register for the current mode
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} ; Store the register state
mov R0,#5 ; ExceptionType
ldr R1,CommonExceptionEntry
bx R1
IrqEntry
sub LR,LR,#4
srsfd #0x13! ; Store return state on SVC stack
cps #0x13 ; Switch to SVC for common stack
stmfd SP!,{LR} ; Store the link register for the current mode
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} ; Store the register state
mov R0,#6 ; ExceptionType
ldr R1,CommonExceptionEntry
bx R1
FiqEntry
sub LR,LR,#4
srsfd #0x13! ; Store return state on SVC stack
cps #0x13 ; Switch to SVC for common stack
stmfd SP!,{LR} ; Store the link register for the current mode
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR
stmfd SP!,{R0-R12} ; Store the register state
; Since we have already switch to SVC R8_fiq - R12_fiq
; never get used or saved
mov R0,#7 ; ExceptionType
ldr R1,CommonExceptionEntry
bx R1
//
// This gets patched by the C code that patches in the vector table
//
CommonExceptionEntry
dcd AsmCommonExceptionEntry
ExceptionHandlersEnd
//
// This code runs from CpuDxe driver loaded address. It is patched into
// CommonExceptionEntry.
//
AsmCommonExceptionEntry
mrc p15, 0, R1, c6, c0, 2 ; Read IFAR
str R1, [SP, #0x50] ; Store it in EFI_SYSTEM_CONTEXT_ARM.IFAR
mrc p15, 0, R1, c5, c0, 1 ; Read IFSR
str R1, [SP, #0x4c] ; Store it in EFI_SYSTEM_CONTEXT_ARM.IFSR
mrc p15, 0, R1, c6, c0, 0 ; Read DFAR
str R1, [SP, #0x48] ; Store it in EFI_SYSTEM_CONTEXT_ARM.DFAR
mrc p15, 0, R1, c5, c0, 0 ; Read DFSR
str R1, [SP, #0x44] ; Store it in EFI_SYSTEM_CONTEXT_ARM.DFSR
ldr R1, [SP, #0x5c] ; srsfd saved pre-exception CPSR on the stack
str R1, [SP, #0x40] ; Store it in EFI_SYSTEM_CONTEXT_ARM.CPSR
add R2, SP, #0x38 ; Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR
and R3, R1, #0x1f ; Check CPSR to see if User or System Mode
cmp R3, #0x1f ; if ((CPSR == 0x10) || (CPSR == 0x1f))
cmpne R3, #0x10 ;
stmeqed R2, {lr}^ ; save unbanked lr
; else
stmneed R2, {lr} ; save SVC lr
ldr R5, [SP, #0x58] ; PC is the LR pushed by srsfd
; Check to see if we have to adjust for Thumb entry
sub r4, r0, #1 ; if (ExceptionType == 1 || ExceptionType == 2)) {
cmp r4, #1 ; // UND & SVC have different LR adjust for Thumb
bhi NoAdjustNeeded
tst r1, #0x20 ; if ((CPSR & T)) == T) { // Thumb Mode on entry
addne R5, R5, #2 ; PC += 2;
strne R5,[SP,#0x58] ; Update LR value pushed by srsfd
NoAdjustNeeded
str R5, [SP, #0x3c] ; Store it in EFI_SYSTEM_CONTEXT_ARM.PC
add R1, SP, #0x60 ; We pushed 0x60 bytes on the stack
str R1, [SP, #0x34] ; Store it in EFI_SYSTEM_CONTEXT_ARM.SP
; R0 is ExceptionType
mov R1,SP ; R1 is SystemContext
#if (FixedPcdGet32(PcdVFPEnabled))
vpush {d0-d15} ; save vstm registers in case they are used in optimizations
#endif
mov R4, SP ; Save current SP
tst R4, #4
subne SP, SP, #4 ; Adjust SP if not 8-byte aligned
/*
VOID
EFIAPI
CommonCExceptionHandler (
IN EFI_EXCEPTION_TYPE ExceptionType, R0
IN OUT EFI_SYSTEM_CONTEXT SystemContext R1
)
*/
blx CommonCExceptionHandler ; Call exception handler
mov SP, R4 ; Restore SP
#if (FixedPcdGet32(PcdVFPEnabled))
vpop {d0-d15}
#endif
ldr R1, [SP, #0x4c] ; Restore EFI_SYSTEM_CONTEXT_ARM.IFSR
mcr p15, 0, R1, c5, c0, 1 ; Write IFSR
ldr R1, [SP, #0x44] ; Restore EFI_SYSTEM_CONTEXT_ARM.DFSR
mcr p15, 0, R1, c5, c0, 0 ; Write DFSR
ldr R1,[SP,#0x3c] ; EFI_SYSTEM_CONTEXT_ARM.PC
str R1,[SP,#0x58] ; Store it back to srsfd stack slot so it can be restored
ldr R1,[SP,#0x40] ; EFI_SYSTEM_CONTEXT_ARM.CPSR
str R1,[SP,#0x5c] ; Store it back to srsfd stack slot so it can be restored
add R3, SP, #0x54 ; Make R3 point to SVC LR saved on entry
add R2, SP, #0x38 ; Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR
and R1, R1, #0x1f ; Check to see if User or System Mode
cmp R1, #0x1f ; if ((CPSR == 0x10) || (CPSR == 0x1f))
cmpne R1, #0x10 ;
ldmeqed R2, {lr}^ ; restore unbanked lr
; else
ldmneed R3, {lr} ; restore SVC lr, via ldmfd SP!, {LR}
ldmfd SP!,{R0-R12} ; Restore general purpose registers
; Exception handler can not change SP
add SP,SP,#0x20 ; Clear out the remaining stack space
ldmfd SP!,{LR} ; restore the link register for this context
rfefd SP! ; return from exception via srsfd stack slot
END

1
ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf
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@ -33,7 +33,6 @@
[Sources.Arm]
Arm/ArmException.c
Arm/ExceptionSupport.asm | RVCT
Arm/ExceptionSupport.S | GCC
[Sources.AARCH64]

1
ArmPkg/Library/ArmExceptionLib/ArmRelocateExceptionLib.inf
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@ -28,7 +28,6 @@
[Sources.Arm]
Arm/ArmException.c
Arm/ExceptionSupport.asm | RVCT
Arm/ExceptionSupport.S | GCC
[Sources.AARCH64]

46
ArmPkg/Library/ArmHvcLib/Arm/ArmHvc.asm
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@ -1,46 +0,0 @@
//
// Copyright (c) 2012-2014, ARM Limited. All rights reserved.
// Copyright (c) 2014, Linaro Limited. All rights reserved.
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
//
INCLUDE AsmMacroExport.inc
RVCT_ASM_EXPORT ArmCallHvc
push {r4-r8}
// r0 will be popped just after the HVC call
push {r0}
// Load the HVC arguments values into the appropriate registers
ldr r7, [r0, #28]
ldr r6, [r0, #24]
ldr r5, [r0, #20]
ldr r4, [r0, #16]
ldr r3, [r0, #12]
ldr r2, [r0, #8]
ldr r1, [r0, #4]
ldr r0, [r0, #0]
hvc #0
// Pop the ARM_HVC_ARGS structure address from the stack into r8
pop {r8}
// Load the HVC returned values into the appropriate registers
// A HVC call can return up to 4 values - we do not need to store back r4-r7.
str r3, [r8, #12]
str r2, [r8, #8]
str r1, [r8, #4]
str r0, [r8, #0]
mov r0, r8
// Restore the registers r4-r8
pop {r4-r8}
bx lr
END

4
ArmPkg/Library/ArmHvcLib/ArmHvcLib.inf
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@ -15,7 +15,6 @@
LIBRARY_CLASS = ArmHvcLib
[Sources.ARM]
Arm/ArmHvc.asm | RVCT
Arm/ArmHvc.S | GCC
[Sources.AARCH64]
@ -24,6 +23,3 @@
[Packages]
MdePkg/MdePkg.dec
ArmPkg/ArmPkg.dec
[BuildOptions]
RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu Cortex-A15

174
ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm
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@ -1,174 +0,0 @@
//------------------------------------------------------------------------------
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
// Copyright (c) 2011 - 2016, ARM Limited. All rights reserved.
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
//------------------------------------------------------------------------------
INCLUDE AsmMacroIoLib.inc
INCLUDE AsmMacroExport.inc
RVCT_ASM_EXPORT ArmReadMidr
mrc p15,0,R0,c0,c0,0
bx LR
RVCT_ASM_EXPORT ArmCacheInfo
mrc p15,0,R0,c0,c0,1
bx LR
RVCT_ASM_EXPORT ArmGetInterruptState
mrs R0,CPSR
tst R0,#0x80 // Check if IRQ is enabled.
moveq R0,#1
movne R0,#0
bx LR
RVCT_ASM_EXPORT ArmGetFiqState
mrs R0,CPSR
tst R0,#0x40 // Check if FIQ is enabled.
moveq R0,#1
movne R0,#0
bx LR
RVCT_ASM_EXPORT ArmSetDomainAccessControl
mcr p15,0,r0,c3,c0,0
bx lr
RVCT_ASM_EXPORT CPSRMaskInsert
stmfd sp!, {r4-r12, lr} // save all the banked registers
mov r3, sp // copy the stack pointer into a non-banked register
mrs r2, cpsr // read the cpsr
bic r2, r2, r0 // clear mask in the cpsr
and r1, r1, r0 // clear bits outside the mask in the input
orr r2, r2, r1 // set field
msr cpsr_cxsf, r2 // write back cpsr (may have caused a mode switch)
isb
mov sp, r3 // restore stack pointer
ldmfd sp!, {r4-r12, lr} // restore registers
bx lr // return (hopefully thumb-safe!) // return (hopefully thumb-safe!)
RVCT_ASM_EXPORT CPSRRead
mrs r0, cpsr
bx lr
RVCT_ASM_EXPORT ArmReadCpacr
mrc p15, 0, r0, c1, c0, 2
bx lr
RVCT_ASM_EXPORT ArmWriteCpacr
mcr p15, 0, r0, c1, c0, 2
isb
bx lr
RVCT_ASM_EXPORT ArmWriteAuxCr
mcr p15, 0, r0, c1, c0, 1
bx lr
RVCT_ASM_EXPORT ArmReadAuxCr
mrc p15, 0, r0, c1, c0, 1
bx lr
RVCT_ASM_EXPORT ArmSetTTBR0
mcr p15,0,r0,c2,c0,0
isb
bx lr
RVCT_ASM_EXPORT ArmSetTTBCR
mcr p15, 0, r0, c2, c0, 2
isb
bx lr
RVCT_ASM_EXPORT ArmGetTTBR0BaseAddress
mrc p15,0,r0,c2,c0,0
MOV32 r1, 0xFFFFC000
and r0, r0, r1
isb
bx lr
//
//VOID
//ArmUpdateTranslationTableEntry (
// IN VOID *TranslationTableEntry // R0
// IN VOID *MVA // R1
// );
RVCT_ASM_EXPORT ArmUpdateTranslationTableEntry
mcr p15,0,R0,c7,c14,1 // DCCIMVAC Clean data cache by MVA
dsb
mcr p15,0,R1,c8,c7,1 // TLBIMVA TLB Invalidate MVA
mcr p15,0,R9,c7,c5,6 // BPIALL Invalidate Branch predictor array. R9 == NoOp
dsb
isb
bx lr
RVCT_ASM_EXPORT ArmInvalidateTlb
mov r0,#0
mcr p15,0,r0,c8,c7,0
mcr p15,0,R9,c7,c5,6 // BPIALL Invalidate Branch predictor array. R9 == NoOp
dsb
isb
bx lr
RVCT_ASM_EXPORT ArmReadScr
mrc p15, 0, r0, c1, c1, 0
bx lr
RVCT_ASM_EXPORT ArmWriteScr
mcr p15, 0, r0, c1, c1, 0
isb
bx lr
RVCT_ASM_EXPORT ArmReadHVBar
mrc p15, 4, r0, c12, c0, 0
bx lr
RVCT_ASM_EXPORT ArmWriteHVBar
mcr p15, 4, r0, c12, c0, 0
bx lr
RVCT_ASM_EXPORT ArmReadMVBar
mrc p15, 0, r0, c12, c0, 1
bx lr
RVCT_ASM_EXPORT ArmWriteMVBar
mcr p15, 0, r0, c12, c0, 1
bx lr
RVCT_ASM_EXPORT ArmCallWFE
wfe
bx lr
RVCT_ASM_EXPORT ArmCallSEV
sev
bx lr
RVCT_ASM_EXPORT ArmReadSctlr
mrc p15, 0, r0, c1, c0, 0 // Read SCTLR into R0 (Read control register configuration data)
bx lr
RVCT_ASM_EXPORT ArmWriteSctlr
mcr p15, 0, r0, c1, c0, 0
bx lr
RVCT_ASM_EXPORT ArmReadCpuActlr
mrc p15, 0, r0, c1, c0, 1
bx lr
RVCT_ASM_EXPORT ArmWriteCpuActlr
mcr p15, 0, r0, c1, c0, 1
dsb
isb
bx lr
RVCT_ASM_EXPORT ArmGetPhysicalAddressBits
mrc p15, 0, r0, c0, c1, 4 ; MMFR0
and r0, r0, #0xf ; VMSA [3:0]
cmp r0, #5 ; >= 5 implies LPAE support
movlt r0, #32 ; 32 bits if no LPAE
movge r0, #40 ; 40 bits if LPAE
bx lr
END

107
ArmPkg/Library/ArmLib/Arm/ArmLibSupportV7.asm
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@ -1,107 +0,0 @@
//------------------------------------------------------------------------------
//
// Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
// Copyright (c) 2011-2013, ARM Limited. All rights reserved.
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
//------------------------------------------------------------------------------
INCLUDE AsmMacroExport.inc
//------------------------------------------------------------------------------
RVCT_ASM_EXPORT ArmIsMpCore
mrc p15,0,R0,c0,c0,5
// Get Multiprocessing extension (bit31) & U bit (bit30)
and R0, R0, #0xC0000000
// if (bit31 == 1) && (bit30 == 0) then the processor is part of a multiprocessor system
cmp R0, #0x80000000
moveq R0, #1
movne R0, #0
bx LR
RVCT_ASM_EXPORT ArmEnableAsynchronousAbort
cpsie a
isb
bx LR
RVCT_ASM_EXPORT ArmDisableAsynchronousAbort
cpsid a
isb
bx LR
RVCT_ASM_EXPORT ArmEnableIrq
cpsie i
isb
bx LR
RVCT_ASM_EXPORT ArmDisableIrq
cpsid i
isb
bx LR
RVCT_ASM_EXPORT ArmEnableFiq
cpsie f
isb
bx LR
RVCT_ASM_EXPORT ArmDisableFiq
cpsid f
isb
bx LR
RVCT_ASM_EXPORT ArmEnableInterrupts
cpsie if
isb
bx LR
RVCT_ASM_EXPORT ArmDisableInterrupts
cpsid if
isb
bx LR
RVCT_ASM_EXPORT ArmReadIdMmfr4
mrc p15,0,r0,c0,c2,6 ; Read ID_MMFR4 Register
bx LR
// UINTN
// ReadCCSIDR (
// IN UINT32 CSSELR
// )
RVCT_ASM_EXPORT ReadCCSIDR
mcr p15,2,r0,c0,c0,0 ; Write Cache Size Selection Register (CSSELR)
isb
mrc p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)
bx lr
// UINT32
// ReadCCSIDR2 (
// IN UINT32 CSSELR
// )
RVCT_ASM_EXPORT ReadCCSIDR2
mcr p15,2,r0,c0,c0,0 ; Write Cache Size Selection Register (CSSELR)
isb
mrc p15,1,r0,c0,c0,2 ; Read current CP15 Cache Size ID Register (CCSIDR2)
bx lr
// UINT32
// ReadCLIDR (
// IN UINT32 CSSELR
// )
RVCT_ASM_EXPORT ReadCLIDR
mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register
bx lr
RVCT_ASM_EXPORT ArmReadNsacr
mrc p15, 0, r0, c1, c1, 2
bx lr
RVCT_ASM_EXPORT ArmWriteNsacr
mcr p15, 0, r0, c1, c1, 2
bx lr
END

93
ArmPkg/Library/ArmLib/Arm/ArmV7ArchTimerSupport.asm
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@ -1,93 +0,0 @@
//------------------------------------------------------------------------------
//
// Copyright (c) 2011, ARM Limited. All rights reserved.
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
//------------------------------------------------------------------------------
INCLUDE AsmMacroExport.inc
PRESERVE8
RVCT_ASM_EXPORT ArmReadCntFrq
mrc p15, 0, r0, c14, c0, 0 ; Read CNTFRQ
bx lr
RVCT_ASM_EXPORT ArmWriteCntFrq
mcr p15, 0, r0, c14, c0, 0 ; Write to CNTFRQ
bx lr
RVCT_ASM_EXPORT ArmReadCntPct
mrrc p15, 0, r0, r1, c14 ; Read CNTPT (Physical counter register)
bx lr
RVCT_ASM_EXPORT ArmReadCntkCtl
mrc p15, 0, r0, c14, c1, 0 ; Read CNTK_CTL (Timer PL1 Control Register)
bx lr
RVCT_ASM_EXPORT ArmWriteCntkCtl
mcr p15, 0, r0, c14, c1, 0 ; Write to CNTK_CTL (Timer PL1 Control Register)
bx lr
RVCT_ASM_EXPORT ArmReadCntpTval
mrc p15, 0, r0, c14, c2, 0 ; Read CNTP_TVAL (PL1 physical timer value register)
bx lr
RVCT_ASM_EXPORT ArmWriteCntpTval
mcr p15, 0, r0, c14, c2, 0 ; Write to CNTP_TVAL (PL1 physical timer value register)
bx lr
RVCT_ASM_EXPORT ArmReadCntpCtl
mrc p15, 0, r0, c14, c2, 1 ; Read CNTP_CTL (PL1 Physical Timer Control Register)
bx lr
RVCT_ASM_EXPORT ArmWriteCntpCtl
mcr p15, 0, r0, c14, c2, 1 ; Write to CNTP_CTL (PL1 Physical Timer Control Register)
bx lr
RVCT_ASM_EXPORT ArmReadCntvTval
mrc p15, 0, r0, c14, c3, 0 ; Read CNTV_TVAL (Virtual Timer Value register)
bx lr
RVCT_ASM_EXPORT ArmWriteCntvTval
mcr p15, 0, r0, c14, c3, 0 ; Write to CNTV_TVAL (Virtual Timer Value register)
bx lr
RVCT_ASM_EXPORT ArmReadCntvCtl
mrc p15, 0, r0, c14, c3, 1 ; Read CNTV_CTL (Virtual Timer Control Register)
bx lr
RVCT_ASM_EXPORT ArmWriteCntvCtl
mcr p15, 0, r0, c14, c3, 1 ; Write to CNTV_CTL (Virtual Timer Control Register)
bx lr
RVCT_ASM_EXPORT ArmReadCntvCt
mrrc p15, 1, r0, r1, c14 ; Read CNTVCT (Virtual Count Register)
bx lr
RVCT_ASM_EXPORT ArmReadCntpCval
mrrc p15, 2, r0, r1, c14 ; Read CNTP_CTVAL (Physical Timer Compare Value Register)
bx lr
RVCT_ASM_EXPORT ArmWriteCntpCval
mcrr p15, 2, r0, r1, c14 ; Write to CNTP_CTVAL (Physical Timer Compare Value Register)
bx lr
RVCT_ASM_EXPORT ArmReadCntvCval
mrrc p15, 3, r0, r1, c14 ; Read CNTV_CTVAL (Virtual Timer Compare Value Register)
bx lr
RVCT_ASM_EXPORT ArmWriteCntvCval
mcrr p15, 3, r0, r1, c14 ; write to CNTV_CTVAL (Virtual Timer Compare Value Register)
bx lr
RVCT_ASM_EXPORT ArmReadCntvOff
mrrc p15, 4, r0, r1, c14 ; Read CNTVOFF (virtual Offset register)
bx lr
RVCT_ASM_EXPORT ArmWriteCntvOff
mcrr p15, 4, r0, r1, c14 ; Write to CNTVOFF (Virtual Offset register)
bx lr
END

292
ArmPkg/Library/ArmLib/Arm/ArmV7Support.asm
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@ -1,292 +0,0 @@
//------------------------------------------------------------------------------
//
// Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
// Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
//------------------------------------------------------------------------------
INCLUDE AsmMacroExport.inc
PRESERVE8
DC_ON EQU ( 0x1:SHL:2 )
IC_ON EQU ( 0x1:SHL:12 )
CTRL_M_BIT EQU (1 << 0)
CTRL_C_BIT EQU (1 << 2)
CTRL_B_BIT EQU (1 << 7)
CTRL_I_BIT EQU (1 << 12)
RVCT_ASM_EXPORT ArmInvalidateDataCacheEntryByMVA
mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
bx lr
RVCT_ASM_EXPORT ArmCleanDataCacheEntryByMVA
mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line
bx lr
RVCT_ASM_EXPORT ArmInvalidateInstructionCacheEntryToPoUByMVA
mcr p15, 0, r0, c7, c5, 1 ; invalidate single instruction cache line to PoU
mcr p15, 0, r0, c7, c5, 7 ; invalidate branch predictor
bx lr
RVCT_ASM_EXPORT ArmCleanDataCacheEntryToPoUByMVA
mcr p15, 0, r0, c7, c11, 1 ; clean single data cache line to PoU
bx lr
RVCT_ASM_EXPORT ArmCleanInvalidateDataCacheEntryByMVA
mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
bx lr
RVCT_ASM_EXPORT ArmInvalidateDataCacheEntryBySetWay
mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line
bx lr
RVCT_ASM_EXPORT ArmCleanInvalidateDataCacheEntryBySetWay
mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line
bx lr
RVCT_ASM_EXPORT ArmCleanDataCacheEntryBySetWay
mcr p15, 0, r0, c7, c10, 2 ; Clean this line
bx lr
RVCT_ASM_EXPORT ArmInvalidateInstructionCache
mcr p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
isb
bx LR
RVCT_ASM_EXPORT ArmEnableMmu
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
orr R0,R0,#1 ; Set SCTLR.M bit : Enable MMU
mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
dsb
isb
bx LR
RVCT_ASM_EXPORT ArmDisableMmu
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
bic R0,R0,#1 ; Clear SCTLR.M bit : Disable MMU
mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
mcr p15,0,R0,c8,c7,0 ; TLBIALL : Invalidate unified TLB
mcr p15,0,R0,c7,c5,6 ; BPIALL : Invalidate entire branch predictor array
dsb
isb
bx LR
RVCT_ASM_EXPORT ArmDisableCachesAndMmu
mrc p15, 0, r0, c1, c0, 0 ; Get control register
bic r0, r0, #CTRL_M_BIT ; Disable MMU
bic r0, r0, #CTRL_C_BIT ; Disable D Cache
bic r0, r0, #CTRL_I_BIT ; Disable I Cache
mcr p15, 0, r0, c1, c0, 0 ; Write control register
dsb
isb
bx LR
RVCT_ASM_EXPORT ArmMmuEnabled
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
and R0,R0,#1
bx LR
RVCT_ASM_EXPORT ArmEnableDataCache
ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
orr R0,R0,R1 ; Set SCTLR.C bit : Data and unified caches enabled
mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
dsb
isb
bx LR
RVCT_ASM_EXPORT ArmDisableDataCache
ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
bic R0,R0,R1 ; Clear SCTLR.C bit : Data and unified caches disabled
mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
dsb
isb
bx LR
RVCT_ASM_EXPORT ArmEnableInstructionCache
ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
orr R0,R0,R1 ; Set SCTLR.I bit : Instruction caches enabled
mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
dsb
isb
bx LR
RVCT_ASM_EXPORT ArmDisableInstructionCache
ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit
mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
BIC R0,R0,R1 ; Clear SCTLR.I bit : Instruction caches disabled
mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
isb
bx LR
RVCT_ASM_EXPORT ArmEnableSWPInstruction
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #0x00000400
mcr p15, 0, r0, c1, c0, 0
isb
bx LR
RVCT_ASM_EXPORT ArmEnableBranchPrediction
mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
orr r0, r0, #0x00000800 ;
mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
dsb
isb
bx LR
RVCT_ASM_EXPORT ArmDisableBranchPrediction
mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
bic r0, r0, #0x00000800 ;
mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
dsb
isb
bx LR
RVCT_ASM_EXPORT ArmSetLowVectors
mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
bic r0, r0, #0x00002000 ; clear V bit
mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
isb
bx LR
RVCT_ASM_EXPORT ArmSetHighVectors
mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
orr r0, r0, #0x00002000 ; Set V bit
mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
isb
bx LR
RVCT_ASM_EXPORT ArmV7AllDataCachesOperation
stmfd SP!,{r4-r12, LR}
mov R1, R0 ; Save Function call in R1
mrc p15, 1, R6, c0, c0, 1 ; Read CLIDR
ands R3, R6, #&7000000 ; Mask out all but Level of Coherency (LoC)
mov R3, R3, LSR #23 ; Cache level value (naturally aligned)
beq Finished
mov R10, #0
Loop1
add R2, R10, R10, LSR #1 ; Work out 3xcachelevel
mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level
and R12, R12, #7 ; get those 3 bits alone
cmp R12, #2
blt Skip ; no cache or only instruction cache at this level
mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
isb ; isb to sync the change to the CacheSizeID reg
mrc p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR)
and R2, R12, #&7 ; extract the line length field
add R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes)
ldr R4, =0x3FF
ands R4, R4, R12, LSR #3 ; R4 is the max number on the way size (right aligned)
clz R5, R4 ; R5 is the bit position of the way size increment
ldr R7, =0x00007FFF
ands R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned)
Loop2
mov R9, R4 ; R9 working copy of the max way size (right aligned)
Loop3
orr R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11
orr R0, R0, R7, LSL R2 ; factor in the index number
blx R1
subs R9, R9, #1 ; decrement the way number
bge Loop3
subs R7, R7, #1 ; decrement the index
bge Loop2
Skip
add R10, R10, #2 ; increment the cache number
cmp R3, R10
bgt Loop1
Finished
dsb
ldmfd SP!, {r4-r12, lr}
bx LR
RVCT_ASM_EXPORT ArmDataMemoryBarrier
dmb
bx LR
RVCT_ASM_EXPORT ArmDataSynchronizationBarrier
dsb
bx LR
RVCT_ASM_EXPORT ArmInstructionSynchronizationBarrier
isb
bx LR
RVCT_ASM_EXPORT ArmReadVBar
// Set the Address of the Vector Table in the VBAR register
mrc p15, 0, r0, c12, c0, 0
bx lr
RVCT_ASM_EXPORT ArmWriteVBar
// Set the Address of the Vector Table in the VBAR register
mcr p15, 0, r0, c12, c0, 0
// Ensure the SCTLR.V bit is clear
mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
bic r0, r0, #0x00002000 ; clear V bit
mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
isb
bx lr
RVCT_ASM_EXPORT ArmEnableVFP
// Read CPACR (Coprocessor Access Control Register)
mrc p15, 0, r0, c1, c0, 2
// Enable VPF access (Full Access to CP10, CP11) (V* instructions)
orr r0, r0, #0x00f00000
// Write back CPACR (Coprocessor Access Control Register)
mcr p15, 0, r0, c1, c0, 2
isb
// Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
mov r0, #0x40000000
mcr p10,#0x7,r0,c8,c0,#0
bx lr
RVCT_ASM_EXPORT ArmCallWFI
wfi
bx lr
//Note: Return 0 in Uniprocessor implementation
RVCT_ASM_EXPORT ArmReadCbar
mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Register
bx lr
RVCT_ASM_EXPORT ArmReadMpidr
mrc p15, 0, r0, c0, c0, 5 ; read MPIDR
bx lr
RVCT_ASM_EXPORT ArmReadTpidrurw
mrc p15, 0, r0, c13, c0, 2 ; read TPIDRURW
bx lr
RVCT_ASM_EXPORT ArmWriteTpidrurw
mcr p15, 0, r0, c13, c0, 2 ; write TPIDRURW
bx lr
RVCT_ASM_EXPORT ArmIsArchTimerImplemented
mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1
and r0, r0, #0x000F0000
bx lr
RVCT_ASM_EXPORT ArmReadIdPfr1
mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1 Register
bx lr
END

5
ArmPkg/Library/ArmLib/ArmBaseLib.inf
View File

@ -30,11 +30,6 @@
Arm/ArmV7Support.S | GCC
Arm/ArmV7ArchTimerSupport.S | GCC
Arm/ArmLibSupport.asm | RVCT
Arm/ArmLibSupportV7.asm | RVCT
Arm/ArmV7Support.asm | RVCT
Arm/ArmV7ArchTimerSupport.asm | RVCT
[Sources.AARCH64]
AArch64/AArch64Lib.h
AArch64/AArch64Lib.c

26
ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibV7Support.asm
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@ -1,26 +0,0 @@
//------------------------------------------------------------------------------
//
// Copyright (c) 2016, Linaro Limited. All rights reserved.
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
//------------------------------------------------------------------------------
INCLUDE AsmMacroExport.inc
//------------------------------------------------------------------------------
RVCT_ASM_EXPORT ArmHasMpExtensions
mrc p15,0,R0,c0,c0,5
// Get Multiprocessing extension (bit31)
lsr R0, R0, #31
bx LR
RVCT_ASM_EXPORT ArmReadIdMmfr0
mrc p15, 0, r0, c0, c1, 4 ; Read ID_MMFR0 Register
bx lr
END

1
ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
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@ -27,7 +27,6 @@
Arm/ArmMmuLibCore.c
Arm/ArmMmuLibUpdate.c
Arm/ArmMmuLibV7Support.S |GCC
Arm/ArmMmuLibV7Support.asm |RVCT
[Packages]
ArmPkg/ArmPkg.dec

45
ArmPkg/Library/ArmSmcLib/Arm/ArmSmc.asm
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@ -1,45 +0,0 @@
//
// Copyright (c) 2012-2014, ARM Limited. All rights reserved.
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
//
INCLUDE AsmMacroExport.inc
RVCT_ASM_EXPORT ArmCallSmc
push {r4-r8}
// r0 will be popped just after the SMC call
push {r0}
// Load the SMC arguments values into the appropriate registers
ldr r7, [r0, #28]
ldr r6, [r0, #24]
ldr r5, [r0, #20]
ldr r4, [r0, #16]
ldr r3, [r0, #12]
ldr r2, [r0, #8]
ldr r1, [r0, #4]
ldr r0, [r0, #0]
smc #0
// Pop the ARM_SMC_ARGS structure address from the stack into r8
pop {r8}
// Load the SMC returned values into the appropriate registers
// A SMC call can return up to 4 values - we do not need to store back r4-r7.
str r3, [r8, #12]
str r2, [r8, #8]
str r1, [r8, #4]
str r0, [r8, #0]
mov r0, r8
// Restore the registers r4-r8
pop {r4-r8}
bx lr
END

4
ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
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@ -14,7 +14,6 @@
LIBRARY_CLASS = ArmSmcLib
[Sources.ARM]
Arm/ArmSmc.asm | RVCT
Arm/ArmSmc.S | GCC
[Sources.AARCH64]
@ -26,6 +25,3 @@
[Packages]
MdePkg/MdePkg.dec
ArmPkg/ArmPkg.dec
[BuildOptions]
RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu 7-A.security

36
ArmPkg/Library/ArmSvcLib/Arm/ArmSvc.asm
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@ -1,36 +0,0 @@
//
// Copyright (c) 2016 - 2020, ARM Limited. All rights reserved.
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
//
INCLUDE AsmMacroExport.inc
RVCT_ASM_EXPORT ArmCallSvc
// r0 will be popped just after the SVC call
push {r0, r4-r8}
// Load the SVC arguments values into the appropriate registers
ldm r0, {r0-r7}
svc #0
// Prevent speculative execution beyond svc instruction
dsb nsh
isb
// Load the ARM_SVC_ARGS structure address from the stack into r8
ldr r8, [sp]
// Load the SVC returned values into the appropriate registers
// A SVC call can return up to 4 values - we do not need to store back r4-r7.
stm r8, {r0-r3}
mov r0, r8
// Restore the registers r4-r8
pop {r1, r4-r8}
bx lr
END

1
ArmPkg/Library/ArmSvcLib/ArmSvcLib.inf
View File

@ -14,7 +14,6 @@
LIBRARY_CLASS = ArmSvcLib
[Sources.ARM]
Arm/ArmSvc.asm | RVCT
Arm/ArmSvc.S | GCC
[Sources.AARCH64]

34
ArmPkg/Library/CompilerIntrinsicsLib/Arm/lasr.asm
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@ -1,34 +0,0 @@
//------------------------------------------------------------------------------
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
//------------------------------------------------------------------------------
INCLUDE AsmMacroExport.inc
;
;UINT32
;EFIAPI
;__aeabi_lasr (
; IN UINT32 Dividen
; IN UINT32 Divisor
; );
;
RVCT_ASM_EXPORT __aeabi_lasr
SUBS r3,r2,#0x20
BPL {pc} + 0x18 ; 0x1c
RSB r3,r2,#0x20
LSR r0,r0,r2
ORR r0,r0,r1,LSL r3
ASR r1,r1,r2
BX lr
ASR r0,r1,r3
ASR r1,r1,#31
BX lr
END

36
ArmPkg/Library/CompilerIntrinsicsLib/Arm/llsl.asm
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@ -1,36 +0,0 @@
//------------------------------------------------------------------------------
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
//------------------------------------------------------------------------------
INCLUDE AsmMacroExport.inc
;
;VOID
;EFIAPI
;__aeabi_llsl (
; IN VOID *Destination,
; IN VOID *Source,
; IN UINT32 Size
; );
;
RVCT_ASM_EXPORT __aeabi_llsl
SUBS r3,r2,#0x20
BPL {pc} + 0x18 ; 0x1c
RSB r3,r2,#0x20
LSL r1,r1,r2
ORR r1,r1,r0,LSR r3
LSL r0,r0,r2
BX lr
LSL r1,r0,r3
MOV r0,#0
BX lr
END

46
ArmPkg/Library/CompilerIntrinsicsLib/Arm/memmove.asm
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@ -1,46 +0,0 @@
//------------------------------------------------------------------------------
//
// Copyright (c) 2011-2014, ARM Limited. All rights reserved.
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
//------------------------------------------------------------------------------
INCLUDE AsmMacroExport.inc
;
;VOID
;EFIAPI
;__aeabi_memmove (
; IN VOID *Destination,
; IN CONST VOID *Source,
; IN UINT32 Size
; );
;
RVCT_ASM_EXPORT __aeabi_memmove
CMP r2, #0
BXEQ lr
CMP r0, r1
BXEQ lr
BHI memmove_backward
memmove_forward
LDRB r3, [r1], #1
STRB r3, [r0], #1
SUBS r2, r2, #1
BNE memmove_forward
BX lr
memmove_backward
add r0, r2
add r1, r2
memmove_backward_loop
LDRB r3, [r1, #-1]!
STRB r3, [r0, #-1]!
SUBS r2, r2, #1
BNE memmove_backward_loop
BX lr
END

43
ArmPkg/Library/CompilerIntrinsicsLib/Arm/mullu.asm
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@ -1,43 +0,0 @@
//------------------------------------------------------------------------------
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
//------------------------------------------------------------------------------
EXPORT __ARM_ll_mullu
EXPORT __aeabi_lmul
AREA Math, CODE, READONLY
;
;INT64
;EFIAPI
;__aeabi_lmul (
; IN INT64 Multiplicand
; IN INT32 Multiplier
; );
;
__ARM_ll_mullu
mov r3, #0
// Make upper part of INT64 Multiplier 0 and use __aeabi_lmul
;
;INT64
;EFIAPI
;__aeabi_lmul (
; IN INT64 Multiplicand
; IN INT64 Multiplier
; );
;
__aeabi_lmul
stmdb sp!, {lr}
mov lr, r0
umull r0, ip, r2, lr
mla r1, r2, r1, ip
mla r1, r3, lr, r1
ldmia sp!, {pc}
END

22
ArmPkg/Library/CompilerIntrinsicsLib/Arm/switch.asm
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@ -1,22 +0,0 @@
///------------------------------------------------------------------------------
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
//------------------------------------------------------------------------------
INCLUDE AsmMacroExport.inc
RVCT_ASM_EXPORT __ARM_switch8
LDRB r12,[lr,#-1]
CMP r3,r12
LDRBCC r3,[lr,r3]
LDRBCS r3,[lr,r12]
ADD r12,lr,r3,LSL #1
BX r12
END

58
ArmPkg/Library/CompilerIntrinsicsLib/Arm/uread.asm
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@ -1,58 +0,0 @@
//------------------------------------------------------------------------------
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
//------------------------------------------------------------------------------
INCLUDE AsmMacroExport.inc
;
;UINT32
;EFIAPI
;__aeabi_uread4 (
; IN VOID *Pointer
; );
;
RVCT_ASM_EXPORT __aeabi_uread4
ldrb r1, [r0]
ldrb r2, [r0, #1]
ldrb r3, [r0, #2]
ldrb r0, [r0, #3]
orr r1, r1, r2, lsl #8
orr r1, r1, r3, lsl #16
orr r0, r1, r0, lsl #24
bx lr
;
;UINT64
;EFIAPI
;__aeabi_uread8 (
; IN VOID *Pointer
; );
;
RVCT_ASM_EXPORT __aeabi_uread8
mov r3, r0
ldrb r1, [r3]
ldrb r2, [r3, #1]
orr r1, r1, r2, lsl #8
ldrb r2, [r3, #2]
orr r1, r1, r2, lsl #16
ldrb r0, [r3, #3]
orr r0, r1, r0, lsl #24
ldrb r1, [r3, #4]
ldrb r2, [r3, #5]
orr r1, r1, r2, lsl #8
ldrb r2, [r3, #6]
orr r1, r1, r2, lsl #16
ldrb r2, [r3, #7]
orr r1, r1, r2, lsl #24
bx lr
END

60
ArmPkg/Library/CompilerIntrinsicsLib/Arm/uwrite.asm
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@ -1,60 +0,0 @@
//------------------------------------------------------------------------------
//
// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
//------------------------------------------------------------------------------
INCLUDE AsmMacroExport.inc
;
;UINT32
;EFIAPI
;__aeabi_uwrite4 (
; IN UINT32 Data,
; IN VOID *Pointer
; );
;
;
RVCT_ASM_EXPORT __aeabi_uwrite4
mov r2, r0, lsr #8
strb r0, [r1]
strb r2, [r1, #1]
mov r2, r0, lsr #16
strb r2, [r1, #2]
mov r2, r0, lsr #24
strb r2, [r1, #3]
bx lr
;
;UINT64
;EFIAPI
;__aeabi_uwrite8 (
; IN UINT64 Data, //r0-r1
; IN VOID *Pointer //r2
; );
;
;
RVCT_ASM_EXPORT __aeabi_uwrite8
mov r3, r0, lsr #8
strb r0, [r2]
strb r3, [r2, #1]
mov r3, r0, lsr #16
strb r3, [r2, #2]
mov r3, r0, lsr #24
strb r3, [r2, #3]
mov r3, r1, lsr #8
strb r1, [r2, #4]
strb r3, [r2, #5]
mov r3, r1, lsr #16
strb r3, [r2, #6]
mov r3, r1, lsr #24
strb r3, [r2, #7]
bx lr
END

15
ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
View File

@ -18,9 +18,6 @@
LIBRARY_CLASS = CompilerIntrinsicsLib
[Sources]
memcpy.c | RVCT
memset.c | RVCT
memcpy.c | GCC
memset.c | GCC
@ -30,18 +27,6 @@
memmove_ms.c | MSFT
[Sources.ARM]
Arm/mullu.asm | RVCT
Arm/switch.asm | RVCT
Arm/llsr.asm | RVCT
Arm/memmove.asm | RVCT
Arm/uread.asm | RVCT
Arm/uwrite.asm | RVCT
Arm/lasr.asm | RVCT
Arm/llsl.asm | RVCT
Arm/div.asm | RVCT
Arm/uldiv.asm | RVCT
Arm/ldivmod.asm | RVCT
Arm/ashrdi3.S | GCC
Arm/ashldi3.S | GCC
Arm/div.S | GCC