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OvmfPkg/TdxDxe: Clear the registers before tdcall 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4696

Refer to the [GHCI] spec, TDVF should clear the BIT5 for RBP in the mask.
And TDVF should clear the regitsers to avoid leaking secrets to VMM.

Reference:
[GHCI]: TDX Guest-Host-Communication Interface v1.5
https://cdrdv2.intel.com/v1/dl/getContent/726792

Cc: Erdem Aktas <erdemaktas@google.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Michael Roth <michael.roth@amd.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: Isaku Yamahata <isaku.yamahata@intel.com>
Signed-off-by: Ceping Sun <cepingx.sun@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Min Xu <min.m.xu@intel.com>
This commit is contained in:
Ceping Sun 2024-02-27 05:18:33 +08:00 committed by mergify[bot]
parent a1a6da80aa
commit 35f6a2780e
1 changed files with 26 additions and 4 deletions
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30
OvmfPkg/TdxDxe/X64/ApRunLoop.nasm
View File

@ -20,7 +20,7 @@ SECTION .text
BITS 64
%define TDVMCALL_EXPOSE_REGS_MASK 0xffec
%define TDVMCALL_EXPOSE_REGS_MASK 0xffcc
%define TDVMCALL 0x0
%define EXIT_REASON_CPUID 0xa
@ -28,6 +28,30 @@ BITS 64
db 0x66, 0x0f, 0x01, 0xcc
%endmacro
%macro tdcall_regs_preamble 2
mov rax, %1
xor rcx, rcx
mov ecx, %2
; R10 = 0 (standard TDVMCALL)
xor r10d, r10d
; Zero out unused (for standard TDVMCALL) registers to avoid leaking
; secrets to the VMM.
xor esi, esi
xor edi, edi
xor edx, edx
xor ebp, ebp
xor r8d, r8d
xor r9d, r9d
xor r14, r14
xor r15, r15
%endmacro
;
; Relocated Ap Mailbox loop
;
@ -40,11 +64,9 @@ global ASM_PFX(AsmRelocateApMailBoxLoop)
ASM_PFX(AsmRelocateApMailBoxLoop):
AsmRelocateApMailBoxLoopStart:
mov rax, TDVMCALL
mov rcx, TDVMCALL_EXPOSE_REGS_MASK
xor r10, r10
mov r11, EXIT_REASON_CPUID
mov r12, 0xb
tdcall_regs_preamble TDVMCALL, TDVMCALL_EXPOSE_REGS_MASK
tdcall
test r10, r10
jnz Panic