mirror of https://github.com/acidanthera/audk.git
OvmfPkg/TdxDxe: Clear the registers before tdcall
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4696 Refer to the [GHCI] spec, TDVF should clear the BIT5 for RBP in the mask. And TDVF should clear the regitsers to avoid leaking secrets to VMM. Reference: [GHCI]: TDX Guest-Host-Communication Interface v1.5 https://cdrdv2.intel.com/v1/dl/getContent/726792 Cc: Erdem Aktas <erdemaktas@google.com> Cc: James Bottomley <jejb@linux.ibm.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Michael Roth <michael.roth@amd.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Isaku Yamahata <isaku.yamahata@intel.com> Signed-off-by: Ceping Sun <cepingx.sun@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Min Xu <min.m.xu@intel.com>
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@ -20,7 +20,7 @@ SECTION .text
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BITS 64
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BITS 64
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%define TDVMCALL_EXPOSE_REGS_MASK 0xffec
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%define TDVMCALL_EXPOSE_REGS_MASK 0xffcc
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%define TDVMCALL 0x0
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%define TDVMCALL 0x0
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%define EXIT_REASON_CPUID 0xa
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%define EXIT_REASON_CPUID 0xa
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@ -28,6 +28,30 @@ BITS 64
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db 0x66, 0x0f, 0x01, 0xcc
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db 0x66, 0x0f, 0x01, 0xcc
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%endmacro
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%endmacro
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%macro tdcall_regs_preamble 2
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mov rax, %1
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xor rcx, rcx
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mov ecx, %2
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; R10 = 0 (standard TDVMCALL)
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xor r10d, r10d
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; Zero out unused (for standard TDVMCALL) registers to avoid leaking
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; secrets to the VMM.
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xor esi, esi
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xor edi, edi
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xor edx, edx
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xor ebp, ebp
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xor r8d, r8d
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xor r9d, r9d
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xor r14, r14
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xor r15, r15
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%endmacro
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;
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;
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; Relocated Ap Mailbox loop
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; Relocated Ap Mailbox loop
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;
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;
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@ -40,11 +64,9 @@ global ASM_PFX(AsmRelocateApMailBoxLoop)
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ASM_PFX(AsmRelocateApMailBoxLoop):
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ASM_PFX(AsmRelocateApMailBoxLoop):
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AsmRelocateApMailBoxLoopStart:
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AsmRelocateApMailBoxLoopStart:
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mov rax, TDVMCALL
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mov rcx, TDVMCALL_EXPOSE_REGS_MASK
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xor r10, r10
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mov r11, EXIT_REASON_CPUID
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mov r11, EXIT_REASON_CPUID
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mov r12, 0xb
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mov r12, 0xb
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tdcall_regs_preamble TDVMCALL, TDVMCALL_EXPOSE_REGS_MASK
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tdcall
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tdcall
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test r10, r10
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test r10, r10
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jnz Panic
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jnz Panic
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