mirror of https://github.com/acidanthera/audk.git
MdePkg/BaseLib: Add stack switch related definitions for IA32
The new definitions include two structures
IA32_TASK_STATE_SEGMENT
IA32_TSS_DESCRIPTOR
two macros
IA32_GDT_TYPE_TSS
IA32_GDT_ALIGNMENT
and one API
VOID
EFIAPI
AsmWriteTr (
IN UINT16 Selector
);
They're needed to setup task gate and interrupt stack table for stack switch.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Suggested-by: Ayellet Wolman <ayellet.wolman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
Reviewed-by: Jeff Fan <vanjeff_919@hotmail.com>
Reviewed-by: Jiewen.yao@intel.com
This commit is contained in:
Jian J Wang
Star Zeng
parent
408b833049
commit
364a54742f
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@ -6647,6 +6647,8 @@ typedef struct {
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#define IA32_IDT_GATE_TYPE_INTERRUPT_32 0x8E
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#define IA32_IDT_GATE_TYPE_TRAP_32 0x8F
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#define IA32_GDT_TYPE_TSS 0x9
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#define IA32_GDT_ALIGNMENT 8
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#if defined (MDE_CPU_IA32)
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///
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@ -6663,6 +6665,70 @@ typedef union {
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UINT64 Uint64;
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} IA32_IDT_GATE_DESCRIPTOR;
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#pragma pack (1)
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//
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// IA32 Task-State Segment Definition
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//
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typedef struct {
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UINT16 PreviousTaskLink;
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UINT16 Reserved_2;
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UINT32 ESP0;
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UINT16 SS0;
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UINT16 Reserved_10;
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UINT32 ESP1;
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UINT16 SS1;
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UINT16 Reserved_18;
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UINT32 ESP2;
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UINT16 SS2;
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UINT16 Reserved_26;
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UINT32 CR3;
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UINT32 EIP;
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UINT32 EFLAGS;
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UINT32 EAX;
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UINT32 ECX;
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UINT32 EDX;
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UINT32 EBX;
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UINT32 ESP;
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UINT32 EBP;
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UINT32 ESI;
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UINT32 EDI;
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UINT16 ES;
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UINT16 Reserved_74;
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UINT16 CS;
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UINT16 Reserved_78;
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UINT16 SS;
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UINT16 Reserved_82;
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UINT16 DS;
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UINT16 Reserved_86;
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UINT16 FS;
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UINT16 Reserved_90;
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UINT16 GS;
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UINT16 Reserved_94;
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UINT16 LDTSegmentSelector;
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UINT16 Reserved_98;
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UINT16 T;
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UINT16 IOMapBaseAddress;
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} IA32_TASK_STATE_SEGMENT;
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typedef union {
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struct {
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UINT32 LimitLow:16; ///< Segment Limit 15..00
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UINT32 BaseLow:16; ///< Base Address 15..00
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UINT32 BaseMid:8; ///< Base Address 23..16
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UINT32 Type:4; ///< Type (1 0 B 1)
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UINT32 Reserved_43:1; ///< 0
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UINT32 DPL:2; ///< Descriptor Privilege Level
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UINT32 P:1; ///< Segment Present
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UINT32 LimitHigh:4; ///< Segment Limit 19..16
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UINT32 AVL:1; ///< Available for use by system software
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UINT32 Reserved_52:2; ///< 0 0
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UINT32 G:1; ///< Granularity
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UINT32 BaseHigh:8; ///< Base Address 31..24
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} Bits;
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UINT64 Uint64;
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} IA32_TSS_DESCRIPTOR;
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#pragma pack ()
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#endif
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#if defined (MDE_CPU_X64)
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@ -6685,6 +6751,46 @@ typedef union {
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} Uint128;
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} IA32_IDT_GATE_DESCRIPTOR;
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#pragma pack (1)
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//
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// IA32 Task-State Segment Definition
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//
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typedef struct {
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UINT32 Reserved_0;
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UINT64 RSP0;
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UINT64 RSP1;
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UINT64 RSP2;
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UINT64 Reserved_28;
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UINT64 IST[7];
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UINT64 Reserved_92;
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UINT16 Reserved_100;
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UINT16 IOMapBaseAddress;
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} IA32_TASK_STATE_SEGMENT;
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typedef union {
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struct {
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UINT32 LimitLow:16; ///< Segment Limit 15..00
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UINT32 BaseLow:16; ///< Base Address 15..00
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UINT32 BaseMidl:8; ///< Base Address 23..16
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UINT32 Type:4; ///< Type (1 0 B 1)
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UINT32 Reserved_43:1; ///< 0
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UINT32 DPL:2; ///< Descriptor Privilege Level
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UINT32 P:1; ///< Segment Present
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UINT32 LimitHigh:4; ///< Segment Limit 19..16
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UINT32 AVL:1; ///< Available for use by system software
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UINT32 Reserved_52:2; ///< 0 0
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UINT32 G:1; ///< Granularity
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UINT32 BaseMidh:8; ///< Base Address 31..24
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UINT32 BaseHigh:32; ///< Base Address 63..32
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UINT32 Reserved_96:32; ///< Reserved
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} Bits;
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struct {
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UINT64 Uint64;
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UINT64 Uint64_1;
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} Uint128;
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} IA32_TSS_DESCRIPTOR;
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#pragma pack ()
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#endif
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///
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@ -8950,6 +9056,17 @@ AsmRdRand64 (
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OUT UINT64 *Rand
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);
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/**
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Load given selector into TR register
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@param[in] Selector Task segment selector
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**/
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VOID
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EFIAPI
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AsmWriteTr (
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IN UINT16 Selector
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);
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#endif
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#endif
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@ -67,6 +67,8 @@
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BaseLibInternals.h
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[Sources.Ia32]
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Ia32/WriteTr.nasm
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Ia32/Wbinvd.c | MSFT
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Ia32/WriteMm7.c | MSFT
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Ia32/WriteMm6.c | MSFT
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@ -447,6 +449,7 @@
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X64/EnableCache.asm
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X64/DisableCache.nasm
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X64/DisableCache.asm
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X64/WriteTr.nasm
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X64/CpuBreakpoint.c | MSFT
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X64/WriteMsr64.c | MSFT
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@ -0,0 +1,36 @@
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;------------------------------------------------------------------------------ ;
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; Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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; This program and the accompanying materials
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; are licensed and made available under the terms and conditions of the BSD License
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; which accompanies this distribution. The full text of the license may be found at
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; http://opensource.org/licenses/bsd-license.php.
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;
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; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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;
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; Module Name:
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;
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; WriteTr.nasm
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;
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; Abstract:
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;
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; Write TR register
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;
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; Notes:
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;
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;------------------------------------------------------------------------------
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SECTION .text
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;------------------------------------------------------------------------------
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; VOID
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; AsmWriteTr (
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; UINT16 Selector
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; );
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;------------------------------------------------------------------------------
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global ASM_PFX(AsmWriteTr)
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ASM_PFX(AsmWriteTr):
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mov eax, [esp+4]
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ltr ax
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ret
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@ -0,0 +1,37 @@
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;------------------------------------------------------------------------------ ;
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; Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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; This program and the accompanying materials
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; are licensed and made available under the terms and conditions of the BSD License
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; which accompanies this distribution. The full text of the license may be found at
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; http://opensource.org/licenses/bsd-license.php.
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;
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; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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;
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; Module Name:
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;
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; WriteTr.nasm
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;
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; Abstract:
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;
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; Write TR register
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;
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; Notes:
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;
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;------------------------------------------------------------------------------
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DEFAULT REL
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SECTION .text
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;------------------------------------------------------------------------------
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; VOID
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; AsmWriteTr (
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; UINT16 Selector
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; );
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;------------------------------------------------------------------------------
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global ASM_PFX(AsmWriteTr)
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ASM_PFX(AsmWriteTr):
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mov eax, ecx
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ltr ax
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ret
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