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audk
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This check-in fixed the following bugs: 

1.	Pci22.h EFI_LEGACY_EXPANSION_ROM_HEADER definition error
(MdePkg\Include\IndustryStandard\Pci22.h; Tools\CCode\Source\Include\IndustryStandard\Pci22.h)
2.	SetVariable() with DataSize=0xffffffff will cause system hang
(EdkModulePkg\Universal\Variable\RuntimeDxe\Variable.c)
3.	Windows XP Pro & XP HOME Fails to Install from Retail CD
(EdkModulePkg\Bus\Pci\Pcibus\Dxe\PciResourceSupport.c)
4.	Pci22.h header file needs to add some recent type
(MdePkg\Include\IndustryStandard\Pci22.h; Tools\CCode\Source\Include\IndustryStandard\Pci22.h)
5.	Fix issues when ODD cannot boot from Sil0680 PCI-IDE controller
(EdkModulePkg\Bus\Pci\PciBus\Dxe\PciOptionromSupport.c;
EdkModulePkg\Bus\Pci\PciBus\Dxe\PciBus.msa;
EdkModulePkg\ EdkModulePkg.spd)


git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@1900 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
cwu11 2006-11-06 04:20:32 +00:00
parent 05b52e9665
commit 3681d193ed
6 changed files with 298 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
EdkModulePkg/Bus/Pci/PciBus/Dxe/PciBus.msa
View File

@ -56,6 +56,9 @@
<LibraryClass Usage="ALWAYS_CONSUMED">
<Keyword>PeCoffGetEntryPointLib</Keyword>
</LibraryClass>
<LibraryClass Usage="ALWAYS_CONSUMED">
<Keyword>PcdLib</Keyword>
</LibraryClass>
</LibraryClassDefinitions>
<SourceFiles>
<Filename>PciBus.h</Filename>
@ -160,4 +163,16 @@
<ComponentName>gPciBusComponentName</ComponentName>
</Extern>
</Externs>
<PcdCoded>
<PcdEntry PcdItemType="FEATURE_FLAG" Usage="ALWAYS_CONSUMED">
<C_Name>PcdPciIsaEnable</C_Name>
<TokenSpaceGuidCName>gEfiGenericPlatformTokenSpaceGuid</TokenSpaceGuidCName>
<HelpText>Whether ISA decoding is enabled on this platform so we should avoid those aliased resources</HelpText>
</PcdEntry>
<PcdEntry PcdItemType="FEATURE_FLAG" Usage="ALWAYS_CONSUMED">
<C_Name>PcdPciVgaEnable</C_Name>
<TokenSpaceGuidCName>gEfiGenericPlatformTokenSpaceGuid</TokenSpaceGuidCName>
<HelpText>Whether VGA decoding is enabled on this platform so we should avoid those aliased resources</HelpText>
</PcdEntry>
</PcdCoded>
</ModuleSurfaceArea>

41
EdkModulePkg/Bus/Pci/PciBus/Dxe/PciResourceSupport.c
View File

@ -241,11 +241,24 @@ Returns:
LIST_ENTRY *CurrentLink;
PCI_RESOURCE_NODE *Node;
UINT64 offset;
BOOLEAN IsaEnable;
BOOLEAN VGAEnable;
//
// Always assume there is ISA device and VGA device on the platform
// will be customized later
//
IsaEnable = FALSE;
VGAEnable = FALSE;
if (FeaturePcdGet (PcdPciIsaEnable)){
IsaEnable = TRUE;
}
if (FeaturePcdGet (PcdPciVgaEnable)){
VGAEnable = TRUE;
}
Aperture = 0;
if (!Bridge) {
@ -278,6 +291,34 @@ Returns:
// become too limited to meet the requirement of most of devices.
//
if (IsaEnable || VGAEnable) {
if (!IS_PCI_BRIDGE (&(Node->PciDev->Pci)) && !IS_CARDBUS_BRIDGE (&(Node->PciDev->Pci))) {
//
// Check if there is need to support ISA/VGA decoding
// If so, we need to avoid isa/vga aliasing range
//
if (IsaEnable) {
SkipIsaAliasAperture (
&Aperture,
Node->Length
);
offset = Aperture & (Node->Alignment);
if (offset) {
Aperture = Aperture + (Node->Alignment + 1) - offset;
}
} else if (VGAEnable) {
SkipVGAAperture (
&Aperture,
Node->Length
);
offset = Aperture & (Node->Alignment);
if (offset) {
Aperture = Aperture + (Node->Alignment + 1) - offset;
}
}
}
}
Node->Offset = Aperture;
//

20
EdkModulePkg/EdkModulePkg.spd
View File

@ -16,7 +16,7 @@
<Specification>FRAMEWORK_BUILD_PACKAGING_SPECIFICATION 0x00000052</Specification>
</SpdHeader>
<PackageDefinitions>
<ReadOnly>true</ReadOnly>
<ReadOnly>false</ReadOnly>
<RePackage>false</RePackage>
</PackageDefinitions>
<LibraryClassDeclarations>
@ -1135,5 +1135,23 @@
<DefaultValue>FALSE</DefaultValue>
<HelpText>If TRUE, then the Device Path From Text Protocol should be produced by the platform</HelpText>
</PcdEntry>
<PcdEntry>
<C_Name>PcdPciIsaEnable</C_Name>
<Token>0x00010039</Token>
<TokenSpaceGuidCName>gEfiGenericPlatformTokenSpaceGuid</TokenSpaceGuidCName>
<DatumType>BOOLEAN</DatumType>
<ValidUsage>FEATURE_FLAG</ValidUsage>
<DefaultValue>FALSE</DefaultValue>
<HelpText>This is a switch to enable ISA</HelpText>
</PcdEntry>
<PcdEntry>
<C_Name>PcdPciVgaEnable</C_Name>
<Token>0x0001003a</Token>
<TokenSpaceGuidCName>gEfiGenericPlatformTokenSpaceGuid</TokenSpaceGuidCName>
<DatumType>BOOLEAN</DatumType>
<ValidUsage>FEATURE_FLAG</ValidUsage>
<DefaultValue>FALSE</DefaultValue>
<HelpText>Whether VGA decoding is enabled on this platform so we should avoid those aliased resources</HelpText>
</PcdEntry>
</PcdDeclarations>
</PackageSurfaceArea>

21
EdkModulePkg/Universal/Variable/RuntimeDxe/Variable.c
View File

@ -15,7 +15,7 @@ Module Name:
Abstract:
Provide support functions for variable services.
Revision History
--*/
@ -125,8 +125,7 @@ Arguments:
Returns:
EFI_INVALID_PARAMETER - Parameters not valid
EFI_SUCCESS - Variable store successfully updated
EFI STATUS
--*/
{
@ -177,10 +176,11 @@ Returns:
if ((DataPtr + DataSize) >= ((UINTN) ((UINT8 *) VolatileBase + VolatileBase->Size))) {
return EFI_INVALID_PARAMETER;
}
//
// If Volatile Variable just do a simple mem copy.
//
}
//
// If Volatile Variable just do a simple mem copy.
//
if (Volatile) {
CopyMem ((UINT8 *) ((UINTN) DataPtr), Buffer, DataSize);
return EFI_SUCCESS;
}
@ -212,7 +212,9 @@ Returns:
&CurrWriteSize,
CurrBuffer
);
return Status;
if (EFI_ERROR (Status)) {
return Status;
}
} else {
Size = (UINT32) (LinearOffset + PtrBlockMapEntry->BlockLength - CurrWritePtr);
Status = EfiFvbWriteBlock (
@ -813,7 +815,8 @@ Returns:
// The size of the VariableName, including the Unicode Null in bytes plus
// the DataSize is limited to maximum size of MAX_VARIABLE_SIZE (1024) bytes.
//
else if (sizeof (VARIABLE_HEADER) + ArrayLength (VariableName) + DataSize > MAX_VARIABLE_SIZE) {
else if ((DataSize > MAX_VARIABLE_SIZE) ||
(sizeof (VARIABLE_HEADER) + ArrayLength (VariableName) + DataSize > MAX_VARIABLE_SIZE)) {
return EFI_INVALID_PARAMETER;
}
//

114
MdePkg/Include/IndustryStandard/pci22.h
View File

@ -168,6 +168,65 @@ typedef struct {
#define PCI_CLASS_BRIDGE_RACEWAY 0x08
#define PCI_CLASS_BRIDGE_ISA_PDECODE 0x80
#define PCI_CLASS_ISA_POSITIVE_DECODE 0x80 // obsolete
#define PCI_CLASS_SCC 0x07 // Simple communications controllers
#define PCI_SUBCLASS_SERIAL 0x00
#define PCI_IF_GENERIC_XT 0x00
#define PCI_IF_16450 0x01
#define PCI_IF_16550 0x02
#define PCI_IF_16650 0x03
#define PCI_IF_16750 0x04
#define PCI_IF_16850 0x05
#define PCI_IF_16950 0x06
#define PCI_SUBCLASS_PARALLEL 0x01
#define PCI_IF_PARALLEL_PORT 0x00
#define PCI_IF_BI_DIR_PARALLEL_PORT 0x01
#define PCI_IF_ECP_PARALLEL_PORT 0x02
#define PCI_IF_1284_CONTROLLER 0x03
#define PCI_IF_1284_DEVICE 0xFE
#define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02
#define PCI_SUBCLASS_MODEM 0x03
#define PCI_IF_GENERIC_MODEM 0x00
#define PCI_IF_16450_MODEM 0x01
#define PCI_IF_16550_MODEM 0x02
#define PCI_IF_16650_MODEM 0x03
#define PCI_IF_16750_MODEM 0x04
#define PCI_SUBCLASS_OTHER 0x80
#define PCI_CLASS_SYSTEM_PERIPHERAL 0x08
#define PCI_SUBCLASS_PIC 0x00
#define PCI_IF_8259_PIC 0x00
#define PCI_IF_ISA_PIC 0x01
#define PCI_IF_EISA_PIC 0x02
#define PCI_IF_APIC_CONTROLLER 0x10 // I/O APIC interrupt controller , 32 bye none-prefectable memory.
#define PCI_IF_APIC_CONTROLLER2 0x20
#define PCI_SUBCLASS_TIMER 0x02
#define PCI_IF_8254_TIMER 0x00
#define PCI_IF_ISA_TIMER 0x01
#define PCI_EISA_TIMER 0x02
#define PCI_SUBCLASS_RTC 0x03
#define PCI_IF_GENERIC_RTC 0x00
#define PCI_IF_ISA_RTC 0x00
#define PCI_SUBCLASS_PNP_CONTROLLER 0x04 // HotPlug Controller
#define PCI_CLASS_INPUT_DEVICE 0x09
#define PCI_SUBCLASS_KEYBOARD 0x00
#define PCI_SUBCLASS_PEN 0x01
#define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02
#define PCI_SUBCLASS_SCAN_CONTROLLER 0x03
#define PCI_SUBCLASS_GAMEPORT 0x04
#define PCI_CLASS_DOCKING_STATION 0x0A
#define PCI_CLASS_PROCESSOR 0x0B
#define PCI_SUBCLASS_PROC_386 0x00
#define PCI_SUBCLASS_PROC_486 0x01
#define PCI_SUBCLASS_PROC_PENTIUM 0x02
#define PCI_SUBCLASS_PROC_ALPHA 0x10
#define PCI_SUBCLASS_PROC_POWERPC 0x20
#define PCI_SUBCLASS_PROC_MIPS 0x30
#define PCI_SUBCLASS_PROC_CO_PORC 0x40 // Co-Processor
#define PCI_CLASS_SERIAL 0x0C
#define PCI_CLASS_SERIAL_FIREWIRE 0x00
#define PCI_CLASS_SERIAL_ACCESS_BUS 0x01
@ -176,6 +235,25 @@ typedef struct {
#define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04
#define PCI_CLASS_SERIAL_SMB 0x05
#define PCI_CLASS_WIRELESS 0x0D
#define PCI_SUBCLASS_IRDA 0x00
#define PCI_SUBCLASS_IR 0x01
#define PCI_SUBCLASS_RF 0x02
#define PCI_CLASS_INTELLIGENT_IO 0x0E
#define PCI_CLASS_SATELLITE 0x0F
#define PCI_SUBCLASS_TV 0x01
#define PCI_SUBCLASS_AUDIO 0x02
#define PCI_SUBCLASS_VOICE 0x03
#define PCI_SUBCLASS_DATA 0x04
#define PCI_SECURITY_CONTROLLER 0x10 // Encryption and decryption controller
#define PCI_SUBCLASS_NET_COMPUT 0x00
#define PCI_SUBCLASS_ENTERTAINMENT 0x10
#define PCI_CLASS_DPIO 0x11
#define IS_CLASS1(_p, c) ((_p)->Hdr.ClassCode[2] == (c))
#define IS_CLASS2(_p, c, s) (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))
#define IS_CLASS3(_p, c, s, p) (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))
@ -208,8 +286,8 @@ typedef struct {
#define PCI_DEVICE_ROMBAR 0x30
#define PCI_BRIDGE_ROMBAR 0x38
#define PCI_MAX_BAR 6
#define PCI_MAX_CONFIG_OFFSET 0x100
#define PCI_MAX_BAR 0x0006
#define PCI_MAX_CONFIG_OFFSET 0x0100
//
// bugbug: this is supported in PCI spec v2.3
//
@ -225,6 +303,18 @@ typedef struct {
#define PCI_LATENCY_TIMER_OFFSET 0x0D
#define PCI_HEADER_TYPE_OFFSET 0x0E
#define PCI_BIST_OFFSET 0x0F
#define PCI_BASE_ADDRESSREG_OFFSET 0x10
#define PCI_CARDBUS_CIS_OFFSET 0x28
#define PCI_SVID_OFFSET 0x2C // SubSystem Vendor id
#define PCI_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C
#define PCI_SID_OFFSET 0x2E // SubSystem ID
#define PCI_SUBSYSTEM_ID_OFFSET 0x2E
#define PCI_EXPANSION_ROM_BASE 0x30
#define PCI_CAPBILITY_POINTER_OFFSET 0x34
#define PCI_INT_LINE_OFFSET 0x3C // Interrupt Line Register
#define PCI_INT_PIN_OFFSET 0x3D // Interrupt Pin Register
#define PCI_MAXGNT_OFFSET 0x3E // Max Grant Register
#define PCI_MAXLAT_OFFSET 0x3F // Max Latency Register
#define PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E
#define PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E
@ -328,7 +418,8 @@ typedef struct {
typedef struct {
UINT16 Signature; // 0xaa55
UINT8 Size512;
UINT8 Reserved[15];
UINT8 InitEntryPoint[3];
UINT8 Reserved[0x12];
UINT16 PcirOffset;
} EFI_LEGACY_EXPANSION_ROM_HEADER;
@ -354,6 +445,23 @@ typedef struct {
UINT16 Reserved1;
} PCI_DATA_STRUCTURE;
typedef struct {
UINT32 Signature; // "PCIR"
UINT16 VendorId;
UINT16 DeviceId;
UINT16 DeviceListOffset;
UINT16 Length;
UINT8 Revision;
UINT8 ClassCode[3];
UINT16 ImageLength;
UINT16 CodeRevision;
UINT8 CodeType;
UINT8 Indicator;
UINT16 MaxRuntimeImageLength;
UINT16 ConfigUtilityCodeHeaderOffset;
UINT16 DMTFCLPEntryPointOffset;
} PCI_3_0_DATA_STRUCTURE;
//
// PCI Capability List IDs and records
//

97
Tools/CCode/Source/Include/IndustryStandard/pci22.h
View File

@ -168,6 +168,65 @@ typedef struct {
#define PCI_CLASS_BRIDGE_RACEWAY 0x08
#define PCI_CLASS_BRIDGE_ISA_PDECODE 0x80
#define PCI_CLASS_ISA_POSITIVE_DECODE 0x80 // obsolete
#define PCI_CLASS_SCC 0x07 // Simple communications controllers
#define PCI_SUBCLASS_SERIAL 0x00
#define PCI_IF_GENERIC_XT 0x00
#define PCI_IF_16450 0x01
#define PCI_IF_16550 0x02
#define PCI_IF_16650 0x03
#define PCI_IF_16750 0x04
#define PCI_IF_16850 0x05
#define PCI_IF_16950 0x06
#define PCI_SUBCLASS_PARALLEL 0x01
#define PCI_IF_PARALLEL_PORT 0x00
#define PCI_IF_BI_DIR_PARALLEL_PORT 0x01
#define PCI_IF_ECP_PARALLEL_PORT 0x02
#define PCI_IF_1284_CONTROLLER 0x03
#define PCI_IF_1284_DEVICE 0xFE
#define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02
#define PCI_SUBCLASS_MODEM 0x03
#define PCI_IF_GENERIC_MODEM 0x00
#define PCI_IF_16450_MODEM 0x01
#define PCI_IF_16550_MODEM 0x02
#define PCI_IF_16650_MODEM 0x03
#define PCI_IF_16750_MODEM 0x04
#define PCI_SUBCLASS_OTHER 0x80
#define PCI_CLASS_SYSTEM_PERIPHERAL 0x08
#define PCI_SUBCLASS_PIC 0x00
#define PCI_IF_8259_PIC 0x00
#define PCI_IF_ISA_PIC 0x01
#define PCI_IF_EISA_PIC 0x02
#define PCI_IF_APIC_CONTROLLER 0x10 // I/O APIC interrupt controller , 32 bye none-prefectable memory.
#define PCI_IF_APIC_CONTROLLER2 0x20
#define PCI_SUBCLASS_TIMER 0x02
#define PCI_IF_8254_TIMER 0x00
#define PCI_IF_ISA_TIMER 0x01
#define PCI_EISA_TIMER 0x02
#define PCI_SUBCLASS_RTC 0x03
#define PCI_IF_GENERIC_RTC 0x00
#define PCI_IF_ISA_RTC 0x00
#define PCI_SUBCLASS_PNP_CONTROLLER 0x04 // HotPlug Controller
#define PCI_CLASS_INPUT_DEVICE 0x09
#define PCI_SUBCLASS_KEYBOARD 0x00
#define PCI_SUBCLASS_PEN 0x01
#define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02
#define PCI_SUBCLASS_SCAN_CONTROLLER 0x03
#define PCI_SUBCLASS_GAMEPORT 0x04
#define PCI_CLASS_DOCKING_STATION 0x0A
#define PCI_CLASS_PROCESSOR 0x0B
#define PCI_SUBCLASS_PROC_386 0x00
#define PCI_SUBCLASS_PROC_486 0x01
#define PCI_SUBCLASS_PROC_PENTIUM 0x02
#define PCI_SUBCLASS_PROC_ALPHA 0x10
#define PCI_SUBCLASS_PROC_POWERPC 0x20
#define PCI_SUBCLASS_PROC_MIPS 0x30
#define PCI_SUBCLASS_PROC_CO_PORC 0x40 // Co-Processor
#define PCI_CLASS_SERIAL 0x0C
#define PCI_CLASS_SERIAL_FIREWIRE 0x00
#define PCI_CLASS_SERIAL_ACCESS_BUS 0x01
@ -176,6 +235,25 @@ typedef struct {
#define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04
#define PCI_CLASS_SERIAL_SMB 0x05
#define PCI_CLASS_WIRELESS 0x0D
#define PCI_SUBCLASS_IRDA 0x00
#define PCI_SUBCLASS_IR 0x01
#define PCI_SUBCLASS_RF 0x02
#define PCI_CLASS_INTELLIGENT_IO 0x0E
#define PCI_CLASS_SATELLITE 0x0F
#define PCI_SUBCLASS_TV 0x01
#define PCI_SUBCLASS_AUDIO 0x02
#define PCI_SUBCLASS_VOICE 0x03
#define PCI_SUBCLASS_DATA 0x04
#define PCI_SECURITY_CONTROLLER 0x10 // Encryption and decryption controller
#define PCI_SUBCLASS_NET_COMPUT 0x00
#define PCI_SUBCLASS_ENTERTAINMENT 0x10
#define PCI_CLASS_DPIO 0x11
#define IS_CLASS1(_p, c) ((_p)->Hdr.ClassCode[2] == (c))
#define IS_CLASS2(_p, c, s) (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))
#define IS_CLASS3(_p, c, s, p) (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))
@ -208,8 +286,8 @@ typedef struct {
#define PCI_DEVICE_ROMBAR 0x30
#define PCI_BRIDGE_ROMBAR 0x38
#define PCI_MAX_BAR 6
#define PCI_MAX_CONFIG_OFFSET 0x100
#define PCI_MAX_BAR 0x0006
#define PCI_MAX_CONFIG_OFFSET 0x0100
//
// bugbug: this is supported in PCI spec v2.3
//
@ -225,6 +303,18 @@ typedef struct {
#define PCI_LATENCY_TIMER_OFFSET 0x0D
#define PCI_HEADER_TYPE_OFFSET 0x0E
#define PCI_BIST_OFFSET 0x0F
#define PCI_BASE_ADDRESSREG_OFFSET 0x10
#define PCI_CARDBUS_CIS_OFFSET 0x28
#define PCI_SVID_OFFSET 0x2C // SubSystem Vendor id
#define PCI_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C
#define PCI_SID_OFFSET 0x2E // SubSystem ID
#define PCI_SUBSYSTEM_ID_OFFSET 0x2E
#define PCI_EXPANSION_ROM_BASE 0x30
#define PCI_CAPBILITY_POINTER_OFFSET 0x34
#define PCI_INT_LINE_OFFSET 0x3C // Interrupt Line Register
#define PCI_INT_PIN_OFFSET 0x3D // Interrupt Pin Register
#define PCI_MAXGNT_OFFSET 0x3E // Max Grant Register
#define PCI_MAXLAT_OFFSET 0x3F // Max Latency Register
#define PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E
#define PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E
@ -328,7 +418,8 @@ typedef struct {
typedef struct {
UINT16 Signature; // 0xaa55
UINT8 Size512;
UINT8 Reserved[15];
UINT8 InitEntryPoint[3];
UINT8 Reserved[0x12];
UINT16 PcirOffset;
} EFI_LEGACY_EXPANSION_ROM_HEADER;