mirror of https://github.com/acidanthera/audk.git
ArmPlatformPkg: Fix builds
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11964 6f19259b-4bc3-4df7-8a09-765794883524
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@ -37,6 +37,7 @@
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DevicePathLib
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HobLib
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PerformanceLib
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SerialPortLib
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[Guids]
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gEfiFileInfoGuid
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@ -21,7 +21,7 @@
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.text
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.align 3
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GCC_ASM_EXPORT(ArmPlatformInitializeBootMemory)
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GCC_ASM_EXPORT(ArmPlatformIsMemoryInitialized)
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/**
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Called at the early stage of the Boot phase to know if the memory has already been initialized
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@ -30,33 +30,33 @@ GCC_ASM_IMPORT(PL35xSmcInitialize)
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VersatileExpressSmcConfiguration:
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// NOR Flash 0
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.word PL350_SMC_DIRECT_CMD_ADDR_CS(0)
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.word PL350_SMC_SET_CYCLE_NAND_T_RC(0xA) :OR: PL350_SMC_SET_CYCLE_NAND_T_WC(0x3) :OR: PL350_SMC_SET_CYCLE_NAND_T_REA(0x1) :OR: PL350_SMC_SET_CYCLE_NAND_T_WP(0x7) :OR: PL350_SMC_SET_CYCLE_NAND_T_AR(0x1)
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.word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_ADV
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.word PL350_SMC_SET_CYCLE_NAND_T_RC(0xA) | PL350_SMC_SET_CYCLE_NAND_T_WC(0x3) | PL350_SMC_SET_CYCLE_NAND_T_REA(0x1) | PL350_SMC_SET_CYCLE_NAND_T_WP(0x7) | PL350_SMC_SET_CYCLE_NAND_T_AR(0x1)
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.word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 | PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT | PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT | PL350_SMC_SET_OPMODE_SET_ADV
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// NOR Flash 1
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.word PL350_SMC_DIRECT_CMD_ADDR_CS(4)
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.word PL350_SMC_SET_CYCLE_NAND_T_RC(0xA) :OR: PL350_SMC_SET_CYCLE_NAND_T_WC(0x3) :OR: PL350_SMC_SET_CYCLE_NAND_T_REA(0x1) :OR: PL350_SMC_SET_CYCLE_NAND_T_WP(0x7) :OR: PL350_SMC_SET_CYCLE_NAND_T_AR(0x1)
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.word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_ADV
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.word PL350_SMC_SET_CYCLE_NAND_T_RC(0xA) | PL350_SMC_SET_CYCLE_NAND_T_WC(0x3) | PL350_SMC_SET_CYCLE_NAND_T_REA(0x1) | PL350_SMC_SET_CYCLE_NAND_T_WP(0x7) | PL350_SMC_SET_CYCLE_NAND_T_AR(0x1)
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.word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 | PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT | PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT | PL350_SMC_SET_OPMODE_SET_ADV
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// SRAM
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.word PL350_SMC_DIRECT_CMD_ADDR_CS(2)
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.word PL350_SMC_SET_CYCLE_SRAM_T_RC(0x8) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WC(0x5) :OR: PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WP(0x6) :OR: PL350_SMC_SET_CYCLE_SRAM_T_PC(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_TR(0x1)
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.word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_ADV
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.word PL350_SMC_SET_CYCLE_SRAM_T_RC(0x8) | PL350_SMC_SET_CYCLE_SRAM_T_WC(0x5) | PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x1) | PL350_SMC_SET_CYCLE_SRAM_T_WP(0x6) | PL350_SMC_SET_CYCLE_SRAM_T_PC(0x1) | PL350_SMC_SET_CYCLE_SRAM_T_TR(0x1)
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.word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 | PL350_SMC_SET_OPMODE_SET_ADV
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// Usb/Eth/VRAM
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.word PL350_SMC_DIRECT_CMD_ADDR_CS(3)
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.word PL350_SMC_SET_CYCLE_SRAM_T_RC(0xA) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WC(0xA) :OR: PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x2) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WP(0x2) :OR: PL350_SMC_SET_CYCLE_SRAM_T_PC(0x3) :OR: PL350_SMC_SET_CYCLE_SRAM_T_TR(0x6)
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.word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL350_SMC_SET_OPMODE_SET_WR_SYNC
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.word PL350_SMC_SET_CYCLE_SRAM_T_RC(0xA) | PL350_SMC_SET_CYCLE_SRAM_T_WC(0xA) | PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x2) | PL350_SMC_SET_CYCLE_SRAM_T_WP(0x2) | PL350_SMC_SET_CYCLE_SRAM_T_PC(0x3) | PL350_SMC_SET_CYCLE_SRAM_T_TR(0x6)
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.word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 | PL350_SMC_SET_OPMODE_SET_RD_SYNC | PL350_SMC_SET_OPMODE_SET_WR_SYNC
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// Memory Mapped Peripherals
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.word PL350_SMC_DIRECT_CMD_ADDR_CS(7)
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.word PL350_SMC_SET_CYCLE_SRAM_T_RC(0x6) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WC(0x5) :OR: PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WP(0x2) :OR: PL350_SMC_SET_CYCLE_SRAM_T_PC(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_TR(0x1)
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.word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL350_SMC_SET_OPMODE_SET_WR_SYNC
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.word PL350_SMC_SET_CYCLE_SRAM_T_RC(0x6) | PL350_SMC_SET_CYCLE_SRAM_T_WC(0x5) | PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x1) | PL350_SMC_SET_CYCLE_SRAM_T_WP(0x2) | PL350_SMC_SET_CYCLE_SRAM_T_PC(0x1) | PL350_SMC_SET_CYCLE_SRAM_T_TR(0x1)
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.word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 | PL350_SMC_SET_OPMODE_SET_RD_SYNC | PL350_SMC_SET_OPMODE_SET_WR_SYNC
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// VRAM
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.word PL350_SMC_DIRECT_CMD_ADDR_CS(1)
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.word 0x00049249
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.word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL350_SMC_SET_OPMODE_SET_WR_SYNC
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.word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 | PL350_SMC_SET_OPMODE_SET_RD_SYNC | PL350_SMC_SET_OPMODE_SET_WR_SYNC
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VersatileExpressSmcConfigurationEnd:
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/**
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@ -20,7 +20,7 @@
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INCLUDE AsmMacroIoLib.inc
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EXPORT ArmPlatformInitializeBootMemory
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EXPORT ArmPlatformIsMemoryInitialized
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PRESERVE8
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AREA CTA9x4Helper, CODE, READONLY
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@ -12,8 +12,6 @@
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**/
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#include <PiDxe.h>
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#include <Library/PcdLib.h>
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#include <Library/DebugLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/DevicePathLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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**/
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#include <PiDxe.h>
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#include <Library/PcdLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/DevicePathLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Base.h>
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#include <Library/DebugLib.h>
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#include <Library/LcdPlatformLib.h>
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#include <Library/PcdLib.h>
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#include <Library/UefiLib.h>
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#include <Protocol/DevicePath.h>
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#include <Library/LcdPlatformLib.h>
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//
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// Device structures
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**/
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#include <Library/DebugLib.h>
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#include <Library/IoLib.h>
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#include <Library/LcdPlatformLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/PcdLib.h>
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#include <Drivers/PL111Lcd.h>
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@ -48,6 +48,6 @@ ASM_PFX(PL35xSmcInitialize):
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str r0, [r1, #PL350_SMC_DIRECT_CMD_OFFSET]
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add r2, #0xC
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b ASM_PFX(PL350SmcInitialize)
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b ASM_PFX(PL35xSmcInitialize)
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ASM_FUNCTION_REMOVE_IF_UNREFERENCED
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@ -282,10 +282,10 @@ SP805SetTimerPeriod (
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//
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// WatchdogTicks = (TimerPeriod * SP805_CLOCK_FREQUENCY) / 20 MHz ;
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Ticks64bit = DivU64x32( MultU64x32( TimerPeriod, SP805_CLOCK_FREQUENCY ), 20000000 );
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Ticks64bit = DivU64x32(MultU64x32(TimerPeriod, (UINTN)PcdGet32(PcdSP805WatchdogClockFrequencyInHz)), 20000000);
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// The registers in the SP805 are only 32 bits
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if( Ticks64bit > SP805_MAX_TICKS ) {
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if(Ticks64bit > (UINT64)0xFFFFFFFF) {
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// We could load the watchdog with the maximum supported value but
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// if a smaller value was requested, this could have the watchdog
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// triggering before it was intended.
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IN EFI_PEI_FILE_HANDLE FileHandle,
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IN CONST EFI_PEI_SERVICES **PeiServices
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);
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EFI_STATUS
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EFIAPI
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PlatformPeim (
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VOID
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);
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//
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// Module globals
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ArmPlatformPkg/ArmPlatformPkg.dec
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[LibraryClasses]
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BaseLib
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DebugLib
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IoLib
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ArmLib
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ArmPlatformLib
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ArmMPCoreMailBoxLib
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BaseLib
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DebugLib
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IoLib
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PL390GicNonSecLib
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PrintLib
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SerialPortLib
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[Ppis]
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ArmPlatformPkg/ArmPlatformPkg.dec
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[LibraryClasses]
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ArmLib
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ArmPlatformLib
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BaseLib
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DebugLib
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IoLib
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ArmLib
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ArmPlatformLib
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PrintLib
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SerialPortLib
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[Ppis]
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gEfiTemporaryRamSupportPpiGuid
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ArmPlatformPkg/ArmPlatformPkg.dec
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[LibraryClasses]
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ArmLib
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ArmPlatformLib
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BaseLib
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DebugLib
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IoLib
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ArmLib
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ArmPlatformLib
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PL390GicSecLib
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PrintLib
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SerialPortLib
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[FeaturePcd]
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