ArmPlatformPkg: Fix builds

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11964 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin 2011-07-01 19:51:48 +00:00
parent cb5bf2697d
commit 3723a71a33
14 changed files with 39 additions and 30 deletions

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@ -37,6 +37,7 @@
DevicePathLib
HobLib
PerformanceLib
SerialPortLib
[Guids]
gEfiFileInfoGuid

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@ -21,7 +21,7 @@
.text
.align 3
GCC_ASM_EXPORT(ArmPlatformInitializeBootMemory)
GCC_ASM_EXPORT(ArmPlatformIsMemoryInitialized)
/**
Called at the early stage of the Boot phase to know if the memory has already been initialized

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@ -30,33 +30,33 @@ GCC_ASM_IMPORT(PL35xSmcInitialize)
VersatileExpressSmcConfiguration:
// NOR Flash 0
.word PL350_SMC_DIRECT_CMD_ADDR_CS(0)
.word PL350_SMC_SET_CYCLE_NAND_T_RC(0xA) :OR: PL350_SMC_SET_CYCLE_NAND_T_WC(0x3) :OR: PL350_SMC_SET_CYCLE_NAND_T_REA(0x1) :OR: PL350_SMC_SET_CYCLE_NAND_T_WP(0x7) :OR: PL350_SMC_SET_CYCLE_NAND_T_AR(0x1)
.word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_ADV
.word PL350_SMC_SET_CYCLE_NAND_T_RC(0xA) | PL350_SMC_SET_CYCLE_NAND_T_WC(0x3) | PL350_SMC_SET_CYCLE_NAND_T_REA(0x1) | PL350_SMC_SET_CYCLE_NAND_T_WP(0x7) | PL350_SMC_SET_CYCLE_NAND_T_AR(0x1)
.word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 | PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT | PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT | PL350_SMC_SET_OPMODE_SET_ADV
// NOR Flash 1
.word PL350_SMC_DIRECT_CMD_ADDR_CS(4)
.word PL350_SMC_SET_CYCLE_NAND_T_RC(0xA) :OR: PL350_SMC_SET_CYCLE_NAND_T_WC(0x3) :OR: PL350_SMC_SET_CYCLE_NAND_T_REA(0x1) :OR: PL350_SMC_SET_CYCLE_NAND_T_WP(0x7) :OR: PL350_SMC_SET_CYCLE_NAND_T_AR(0x1)
.word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_ADV
.word PL350_SMC_SET_CYCLE_NAND_T_RC(0xA) | PL350_SMC_SET_CYCLE_NAND_T_WC(0x3) | PL350_SMC_SET_CYCLE_NAND_T_REA(0x1) | PL350_SMC_SET_CYCLE_NAND_T_WP(0x7) | PL350_SMC_SET_CYCLE_NAND_T_AR(0x1)
.word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 | PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT | PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT | PL350_SMC_SET_OPMODE_SET_ADV
// SRAM
.word PL350_SMC_DIRECT_CMD_ADDR_CS(2)
.word PL350_SMC_SET_CYCLE_SRAM_T_RC(0x8) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WC(0x5) :OR: PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WP(0x6) :OR: PL350_SMC_SET_CYCLE_SRAM_T_PC(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_TR(0x1)
.word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_ADV
.word PL350_SMC_SET_CYCLE_SRAM_T_RC(0x8) | PL350_SMC_SET_CYCLE_SRAM_T_WC(0x5) | PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x1) | PL350_SMC_SET_CYCLE_SRAM_T_WP(0x6) | PL350_SMC_SET_CYCLE_SRAM_T_PC(0x1) | PL350_SMC_SET_CYCLE_SRAM_T_TR(0x1)
.word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 | PL350_SMC_SET_OPMODE_SET_ADV
// Usb/Eth/VRAM
.word PL350_SMC_DIRECT_CMD_ADDR_CS(3)
.word PL350_SMC_SET_CYCLE_SRAM_T_RC(0xA) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WC(0xA) :OR: PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x2) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WP(0x2) :OR: PL350_SMC_SET_CYCLE_SRAM_T_PC(0x3) :OR: PL350_SMC_SET_CYCLE_SRAM_T_TR(0x6)
.word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL350_SMC_SET_OPMODE_SET_WR_SYNC
.word PL350_SMC_SET_CYCLE_SRAM_T_RC(0xA) | PL350_SMC_SET_CYCLE_SRAM_T_WC(0xA) | PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x2) | PL350_SMC_SET_CYCLE_SRAM_T_WP(0x2) | PL350_SMC_SET_CYCLE_SRAM_T_PC(0x3) | PL350_SMC_SET_CYCLE_SRAM_T_TR(0x6)
.word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 | PL350_SMC_SET_OPMODE_SET_RD_SYNC | PL350_SMC_SET_OPMODE_SET_WR_SYNC
// Memory Mapped Peripherals
.word PL350_SMC_DIRECT_CMD_ADDR_CS(7)
.word PL350_SMC_SET_CYCLE_SRAM_T_RC(0x6) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WC(0x5) :OR: PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WP(0x2) :OR: PL350_SMC_SET_CYCLE_SRAM_T_PC(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_TR(0x1)
.word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL350_SMC_SET_OPMODE_SET_WR_SYNC
.word PL350_SMC_SET_CYCLE_SRAM_T_RC(0x6) | PL350_SMC_SET_CYCLE_SRAM_T_WC(0x5) | PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x1) | PL350_SMC_SET_CYCLE_SRAM_T_WP(0x2) | PL350_SMC_SET_CYCLE_SRAM_T_PC(0x1) | PL350_SMC_SET_CYCLE_SRAM_T_TR(0x1)
.word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 | PL350_SMC_SET_OPMODE_SET_RD_SYNC | PL350_SMC_SET_OPMODE_SET_WR_SYNC
// VRAM
.word PL350_SMC_DIRECT_CMD_ADDR_CS(1)
.word 0x00049249
.word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL350_SMC_SET_OPMODE_SET_WR_SYNC
.word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 | PL350_SMC_SET_OPMODE_SET_RD_SYNC | PL350_SMC_SET_OPMODE_SET_WR_SYNC
VersatileExpressSmcConfigurationEnd:
/**

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@ -20,7 +20,7 @@
INCLUDE AsmMacroIoLib.inc
EXPORT ArmPlatformInitializeBootMemory
EXPORT ArmPlatformIsMemoryInitialized
PRESERVE8
AREA CTA9x4Helper, CODE, READONLY

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@ -12,8 +12,6 @@
**/
#include <PiDxe.h>
#include <Library/PcdLib.h>
#include <Library/DebugLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DevicePathLib.h>
#include <Library/UefiBootServicesTableLib.h>

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@ -12,7 +12,6 @@
**/
#include <PiDxe.h>
#include <Library/PcdLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DevicePathLib.h>
#include <Library/UefiBootServicesTableLib.h>

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@ -16,10 +16,14 @@
#include <Base.h>
#include <Library/DebugLib.h>
#include <Library/LcdPlatformLib.h>
#include <Library/PcdLib.h>
#include <Library/UefiLib.h>
#include <Protocol/DevicePath.h>
#include <Library/LcdPlatformLib.h>
//
// Device structures

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@ -11,11 +11,8 @@
**/
#include <Library/DebugLib.h>
#include <Library/IoLib.h>
#include <Library/LcdPlatformLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/PcdLib.h>
#include <Drivers/PL111Lcd.h>

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@ -48,6 +48,6 @@ ASM_PFX(PL35xSmcInitialize):
str r0, [r1, #PL350_SMC_DIRECT_CMD_OFFSET]
add r2, #0xC
b ASM_PFX(PL350SmcInitialize)
b ASM_PFX(PL35xSmcInitialize)
ASM_FUNCTION_REMOVE_IF_UNREFERENCED

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@ -282,10 +282,10 @@ SP805SetTimerPeriod (
//
// WatchdogTicks = (TimerPeriod * SP805_CLOCK_FREQUENCY) / 20 MHz ;
Ticks64bit = DivU64x32( MultU64x32( TimerPeriod, SP805_CLOCK_FREQUENCY ), 20000000 );
Ticks64bit = DivU64x32(MultU64x32(TimerPeriod, (UINTN)PcdGet32(PcdSP805WatchdogClockFrequencyInHz)), 20000000);
// The registers in the SP805 are only 32 bits
if( Ticks64bit > SP805_MAX_TICKS ) {
if(Ticks64bit > (UINT64)0xFFFFFFFF) {
// We could load the watchdog with the maximum supported value but
// if a smaller value was requested, this could have the watchdog
// triggering before it was intended.

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@ -33,6 +33,12 @@ InitializePlatformPeim (
IN EFI_PEI_FILE_HANDLE FileHandle,
IN CONST EFI_PEI_SERVICES **PeiServices
);
EFI_STATUS
EFIAPI
PlatformPeim (
VOID
);
//
// Module globals

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@ -37,13 +37,14 @@
ArmPlatformPkg/ArmPlatformPkg.dec
[LibraryClasses]
BaseLib
DebugLib
IoLib
ArmLib
ArmPlatformLib
ArmMPCoreMailBoxLib
BaseLib
DebugLib
IoLib
PL390GicNonSecLib
PrintLib
SerialPortLib
[Ppis]

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@ -37,11 +37,13 @@
ArmPlatformPkg/ArmPlatformPkg.dec
[LibraryClasses]
ArmLib
ArmPlatformLib
BaseLib
DebugLib
IoLib
ArmLib
ArmPlatformLib
PrintLib
SerialPortLib
[Ppis]
gEfiTemporaryRamSupportPpiGuid

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@ -36,12 +36,13 @@
ArmPlatformPkg/ArmPlatformPkg.dec
[LibraryClasses]
ArmLib
ArmPlatformLib
BaseLib
DebugLib
IoLib
ArmLib
ArmPlatformLib
PL390GicSecLib
PrintLib
SerialPortLib
[FeaturePcd]