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ArmPkg/ArmGicLib: select GICv2 mode if SRE is present but unavailable 

Even if the CPU id registers indicate hardware support for the
System Register interface to the GIC, higher exception levels
may disable that interface and only allow access through MMIO.

So move the enabling of the SRE bit to the GIC version detection
routine: if we trigger an exception, we would have anyway at a
later stage, so the net effect is the same. However, if setting
the bit doesn't stick, it means we can switch to MMIO and proceed
normally otherwise.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16344 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Ard Biesheuvel 2014-11-13 16:41:51 +00:00 committed by oliviermartin
parent 77d5dac5c6
commit 37ec4d9af7
3 changed files with 26 additions and 10 deletions
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14
ArmPkg/Drivers/ArmGic/AArch64/ArmGicArchLib.c
View File

@ -15,6 +15,8 @@
#include <Library/ArmLib.h>
#include <Library/ArmGicLib.h>
#include "GicV3/ArmGicV3Lib.h"
ARM_GIC_ARCH_REVISION
EFIAPI
ArmGicGetSupportedArchRevision (
@ -28,7 +30,17 @@ ArmGicGetSupportedArchRevision (
// driver requires SRE. If only Memory mapped access is available we try to
// drive the GIC as a v2.
if (ArmReadIdPfr0 () & AARCH64_PFR0_GIC) {
return ARM_GIC_ARCH_REVISION_3;
// Make sure System Register access is enabled (SRE). This depends on the
// higher privilege level giving us permission, otherwise we will either
// cause an exception here, or the write doesn't stick in which case we need
// to fall back to the GICv2 MMIO interface.
// Note: We do not need to set ICC_SRE_EL2.Enable because the OS is started
// at the same exception level.
// It is the OS responsibility to set this bit.
ArmGicV3SetControlSystemRegisterEnable (ArmGicV3GetControlSystemRegisterEnable () | ICC_SRE_EL2_SRE);
if (ArmGicV3GetControlSystemRegisterEnable () & ICC_SRE_EL2_SRE) {
return ARM_GIC_ARCH_REVISION_3;
}
}
return ARM_GIC_ARCH_REVISION_2;

14
ArmPkg/Drivers/ArmGic/Arm/ArmGicArchLib.c
View File

@ -15,6 +15,8 @@
#include <Library/ArmLib.h>
#include <Library/ArmGicLib.h>
#include "GicV3/ArmGicV3Lib.h"
ARM_GIC_ARCH_REVISION
EFIAPI
ArmGicGetSupportedArchRevision (
@ -28,7 +30,17 @@ ArmGicGetSupportedArchRevision (
// driver requires SRE. If only Memory mapped access is available we try to
// drive the GIC as a v2.
if (ArmReadIdPfr1 () & ARM_PFR1_GIC) {
return ARM_GIC_ARCH_REVISION_3;
// Make sure System Register access is enabled (SRE). This depends on the
// higher privilege level giving us permission, otherwise we will either
// cause an exception here, or the write doesn't stick in which case we need
// to fall back to the GICv2 MMIO interface.
// Note: We do not need to set ICC_SRE_EL2.Enable because the OS is started
// at the same exception level.
// It is the OS responsibility to set this bit.
ArmGicV3SetControlSystemRegisterEnable (ArmGicV3GetControlSystemRegisterEnable () | ICC_SRE_EL2_SRE);
if (ArmGicV3GetControlSystemRegisterEnable () & ICC_SRE_EL2_SRE) {
return ARM_GIC_ARCH_REVISION_3;
}
}
return ARM_GIC_ARCH_REVISION_2;

8
ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c
View File

@ -281,14 +281,6 @@ GicV3DxeInitialize (
}
}
// Make sure System Register access is enabled (SRE). This depends on the
// lower levels giving us permission, otherwise we will cause an exception
// here.
// Note: We do not need to set ICC_SRE_EL2.Enable because the OS is started at the
// same exception level.
// It is the OS responsibility to set this bit.
ArmGicV3SetControlSystemRegisterEnable (ArmGicV3GetControlSystemRegisterEnable () | ICC_SRE_EL2_SRE);
// Set binary point reg to 0x7 (no preemption)
ArmGicV3SetBinaryPointer (0x7);