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IntelFsp2Pkg: Add FspmArchConfigPpi to support Dispatch mode 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1381

In Dispatch mode FSP may consume PPI directly so creating
FSPM_ARCH_CONFIG_PPI to align with FSPM_ARCH_UPD.
Also Keeps new structure size 8 bytes alignment as other
structures.

Test: Verified on internal platform to boot with this PPI
installed successfully.

Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
This commit is contained in:
Chasel, Chiu 2018-12-07 21:18:42 +08:00
parent 66cffa6525
commit 3837e2e038
2 changed files with 58 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

54
IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h Normal file
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@ -0,0 +1,54 @@
/** @file
Header file for FSP-M Arch Config PPI for Dispatch mode
@copyright
Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials are licensed and made available under
the terms and conditions of the BSD License which accompanies this distribution.
The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _FSPM_ARCH_CONFIG_PPI_H_
#define _FSPM_ARCH_CONFIG_PPI_H_
#define FSPM_ARCH_CONFIG_PPI_REVISION 0x1
///
/// Global ID for the FSPM_ARCH_CONFIG_PPI.
///
#define FSPM_ARCH_CONFIG_GUID \
{ \
0x824d5a3a, 0xaf92, 0x4c0c, { 0x9f, 0x19, 0x19, 0x52, 0x6d, 0xca, 0x4a, 0xbb } \
}
///
/// This PPI provides FSP-M Arch Config PPI.
///
typedef struct {
///
/// Revision of the structure
///
UINT8 Revision;
UINT8 Reserved[3];
///
/// Pointer to the non-volatile storage (NVS) data buffer.
/// If it is NULL it indicates the NVS data is not available.
///
VOID *NvsBufferPtr;
///
/// Size of memory to be reserved by FSP below "top
/// of low usable memory" for bootloader usage.
///
UINT32 BootLoaderTolumSize;
UINT8 Reserved1[4];
} FSPM_ARCH_CONFIG_PPI;
extern EFI_GUID gFspmArchConfigPpiGuid;
#endif // _FSPM_ARCH_CONFIG_PPI_H_

5
IntelFsp2Pkg/IntelFsp2Pkg.dec
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@ -1,7 +1,7 @@
## @file
# Provides driver and definitions to build fsp in EDKII bios.
#
# Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials are licensed and made available under
# the terms and conditions of the BSD License that accompanies this distribution.
# The full text of the license may be found at
@ -70,6 +70,9 @@
gFspPerformanceDataGuid = { 0x56ed21b6, 0xba23, 0x429e, { 0x89, 0x32, 0x37, 0x6d, 0x8e, 0x18, 0x2e, 0xe3 } }
gFspEventEndOfFirmwareGuid = { 0xbd44f629, 0xeae7, 0x4198, { 0x87, 0xf1, 0x39, 0xfa, 0xb0, 0xfd, 0x71, 0x7e } }
[Ppis]
gFspmArchConfigPpiGuid = { 0x824d5a3a, 0xaf92, 0x4c0c, { 0x9f, 0x19, 0x19, 0x52, 0x6d, 0xca, 0x4a, 0xbb } }
[PcdsFixedAtBuild]
gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress |0xFED00108|UINT32|0x00000001
gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase |0xFEF00000|UINT32|0x10001001