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MdeModulePkg/XhciDxe: rename "Lenth" to "Length" in TRB structs 

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Baraneedharan Anbazhagan <anbazhagan@hp.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17205 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Feng Tian 2015-04-27 05:25:03 +00:00 committed by erictian
parent 994140183f
commit 39e97c396d
2 changed files with 11 additions and 11 deletions
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12
MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
View File

@ -2,7 +2,7 @@
XHCI transfer scheduling routines. XHCI transfer scheduling routines.
Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved.<BR> Copyright (c) 2011 - 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
@ -295,7 +295,7 @@ XhcCreateTransferTrb (
TrbStart->TrbCtrSetup.wValue = Urb->Request->Value; TrbStart->TrbCtrSetup.wValue = Urb->Request->Value;
TrbStart->TrbCtrSetup.wIndex = Urb->Request->Index; TrbStart->TrbCtrSetup.wIndex = Urb->Request->Index;
TrbStart->TrbCtrSetup.wLength = Urb->Request->Length; TrbStart->TrbCtrSetup.wLength = Urb->Request->Length;
TrbStart->TrbCtrSetup.Lenth = 8; TrbStart->TrbCtrSetup.Length = 8;
TrbStart->TrbCtrSetup.IntTarget = 0; TrbStart->TrbCtrSetup.IntTarget = 0;
TrbStart->TrbCtrSetup.IOC = 1; TrbStart->TrbCtrSetup.IOC = 1;
TrbStart->TrbCtrSetup.IDT = 1; TrbStart->TrbCtrSetup.IDT = 1;
@ -321,7 +321,7 @@ XhcCreateTransferTrb (
TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue; TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
TrbStart->TrbCtrData.TRBPtrLo = XHC_LOW_32BIT(Urb->DataPhy); TrbStart->TrbCtrData.TRBPtrLo = XHC_LOW_32BIT(Urb->DataPhy);
TrbStart->TrbCtrData.TRBPtrHi = XHC_HIGH_32BIT(Urb->DataPhy); TrbStart->TrbCtrData.TRBPtrHi = XHC_HIGH_32BIT(Urb->DataPhy);
TrbStart->TrbCtrData.Lenth = (UINT32) Urb->DataLen; TrbStart->TrbCtrData.Length = (UINT32) Urb->DataLen;
TrbStart->TrbCtrData.TDSize = 0; TrbStart->TrbCtrData.TDSize = 0;
TrbStart->TrbCtrData.IntTarget = 0; TrbStart->TrbCtrData.IntTarget = 0;
TrbStart->TrbCtrData.ISP = 1; TrbStart->TrbCtrData.ISP = 1;
@ -387,7 +387,7 @@ XhcCreateTransferTrb (
TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue; TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT((UINT8 *) Urb->DataPhy + TotalLen); TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT((UINT8 *) Urb->DataPhy + TotalLen);
TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT((UINT8 *) Urb->DataPhy + TotalLen); TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT((UINT8 *) Urb->DataPhy + TotalLen);
TrbStart->TrbNormal.Lenth = (UINT32) Len; TrbStart->TrbNormal.Length = (UINT32) Len;
TrbStart->TrbNormal.TDSize = 0; TrbStart->TrbNormal.TDSize = 0;
TrbStart->TrbNormal.IntTarget = 0; TrbStart->TrbNormal.IntTarget = 0;
TrbStart->TrbNormal.ISP = 1; TrbStart->TrbNormal.ISP = 1;
@ -422,7 +422,7 @@ XhcCreateTransferTrb (
TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue; TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;
TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT((UINT8 *) Urb->DataPhy + TotalLen); TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT((UINT8 *) Urb->DataPhy + TotalLen);
TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT((UINT8 *) Urb->DataPhy + TotalLen); TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT((UINT8 *) Urb->DataPhy + TotalLen);
TrbStart->TrbNormal.Lenth = (UINT32) Len; TrbStart->TrbNormal.Length = (UINT32) Len;
TrbStart->TrbNormal.TDSize = 0; TrbStart->TrbNormal.TDSize = 0;
TrbStart->TrbNormal.IntTarget = 0; TrbStart->TrbNormal.IntTarget = 0;
TrbStart->TrbNormal.ISP = 1; TrbStart->TrbNormal.ISP = 1;
@ -1137,7 +1137,7 @@ XhcCheckUrbResult (
if ((TRBType == TRB_TYPE_DATA_STAGE) || if ((TRBType == TRB_TYPE_DATA_STAGE) ||
(TRBType == TRB_TYPE_NORMAL) || (TRBType == TRB_TYPE_NORMAL) ||
(TRBType == TRB_TYPE_ISOCH)) { (TRBType == TRB_TYPE_ISOCH)) {
CheckedUrb->Completed += (CheckedUrb->DataLen - EvtTrb->Lenth); CheckedUrb->Completed += (CheckedUrb->DataLen - EvtTrb->Length);
} }
break; break;

10
MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.h
View File

@ -2,7 +2,7 @@
This file contains the definition for XHCI host controller schedule routines. This file contains the definition for XHCI host controller schedule routines.
Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved.<BR> Copyright (c) 2011 - 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
@ -224,7 +224,7 @@ typedef struct _TRANSFER_TRB_NORMAL {
UINT32 TRBPtrHi; UINT32 TRBPtrHi;
UINT32 Lenth:17; UINT32 Length:17;
UINT32 TDSize:5; UINT32 TDSize:5;
UINT32 IntTarget:10; UINT32 IntTarget:10;
@ -253,7 +253,7 @@ typedef struct _TRANSFER_TRB_CONTROL_SETUP {
UINT32 wIndex:16; UINT32 wIndex:16;
UINT32 wLength:16; UINT32 wLength:16;
UINT32 Lenth:17; UINT32 Length:17;
UINT32 RsvdZ1:5; UINT32 RsvdZ1:5;
UINT32 IntTarget:10; UINT32 IntTarget:10;
@ -276,7 +276,7 @@ typedef struct _TRANSFER_TRB_CONTROL_DATA {
UINT32 TRBPtrHi; UINT32 TRBPtrHi;
UINT32 Lenth:17; UINT32 Length:17;
UINT32 TDSize:5; UINT32 TDSize:5;
UINT32 IntTarget:10; UINT32 IntTarget:10;
@ -325,7 +325,7 @@ typedef struct _EVT_TRB_TRANSFER {
UINT32 TRBPtrHi; UINT32 TRBPtrHi;
UINT32 Lenth:24; UINT32 Length:24;
UINT32 Completecode:8; UINT32 Completecode:8;
UINT32 CycleBit:1; UINT32 CycleBit:1;