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UefiCpuPkg/PiSmmCpuDxeSmm: Align BSP and AP sync logic for SMI exit 

Below piece of code is the BSP and AP sync logic for SMI exit.
1. AP after finish the scheduled procedure:
  if (SmmCpuFeaturesNeedConfigureMtrrs ()) {
    SmmCpuSyncReleaseBsp ();
    SmmCpuSyncWaitForBsp ();
    ...
  }
  SmmCpuSyncReleaseBsp ();
  SmmCpuSyncWaitForBsp ();
  SmmCpuSyncReleaseBsp ();

2. BSP after return from SmmCoreEntry:
  SmmCpuSyncWaitForAPs ();
  if (SmmCpuFeaturesNeedConfigureMtrrs ()) {
    ReleaseAllAPs ();
    ...
    SmmCpuSyncWaitForAPs ();
  }
  ReleaseAllAPs ();
  SmmCpuSyncWaitForAPs();

This patch is to make BSP same as AP sync logic:
  if (SmmCpuFeaturesNeedConfigureMtrrs ()) {
    SmmCpuSyncWaitForAPs ();
    ReleaseAllAPs ();
    ...
  }
  SmmCpuSyncWaitForAPs ();
  ReleaseAllAPs ();
  SmmCpuSyncWaitForAPs();

With the change, it will be easy to understand the sync flow as
below:
BSP: SmmCpuSyncWaitForAPs  <--  AP: SmmCpuSyncReleaseBsp
BSP: ReleaseAllAPs         -->  AP: SmmCpuSyncWaitForBsp

This patch doesn't have function impact.

Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Zeng Star <star.zeng@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
Reviewed-by: Ray Ni <ray.ni@Intel.com>
This commit is contained in:
Jiaxin Wu 2023-12-15 16:45:38 +08:00 committed by mergify[bot]
parent e1b62f3e28
commit 3a4ec6de01
1 changed files with 10 additions and 10 deletions
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20
UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
View File

@ -627,12 +627,12 @@ BSPHandler (
*mSmmMpSyncData->InsideSmm = FALSE; *mSmmMpSyncData->InsideSmm = FALSE;
ReleaseAllAPs (); ReleaseAllAPs ();
//
// Wait for all APs to complete their pending tasks
//
SmmCpuSyncWaitForAPs (mSmmMpSyncData->SyncContext, ApCount, CpuIndex);
if (SmmCpuFeaturesNeedConfigureMtrrs ()) { if (SmmCpuFeaturesNeedConfigureMtrrs ()) {
//
// Wait for all APs the readiness to program MTRRs
//
SmmCpuSyncWaitForAPs (mSmmMpSyncData->SyncContext, ApCount, CpuIndex);
// //
// Signal APs to restore MTRRs // Signal APs to restore MTRRs
// //
@ -643,13 +643,13 @@ BSPHandler (
// //
SmmCpuFeaturesReenableSmrr (); SmmCpuFeaturesReenableSmrr ();
MtrrSetAllMtrrs (&Mtrrs); MtrrSetAllMtrrs (&Mtrrs);
//
// Wait for all APs to complete MTRR programming
//
SmmCpuSyncWaitForAPs (mSmmMpSyncData->SyncContext, ApCount, CpuIndex);
} }
//
// Wait for all APs to complete their pending tasks including MTRR programming if needed.
//
SmmCpuSyncWaitForAPs (mSmmMpSyncData->SyncContext, ApCount, CpuIndex);
if (mSmmDebugAgentSupport) { if (mSmmDebugAgentSupport) {
// //
// Stop source level debug in BSP handler, the code below will not be // Stop source level debug in BSP handler, the code below will not be