mirror of https://github.com/acidanthera/audk.git
DynamicTablesPkg: Move PCI device Handle object to Arch Common
Move the PCI device Handle object from Arm Namespace to the Arch Common namespace. Correspondingly also update the following modules to reflect the changes introduced by the move: - SRAT generator - ConfigurationManagerObjectParser - Dynamic Plat Repo TokenFixer map. Cc: Pierre Gondois <Pierre.Gondois@arm.com> Cc: Yeo Reum Yun <YeoReum.Yun@arm.com> Cc: AbdulLateef Attar <AbdulLateef.Attar@amd.com> Cc: Jeshua Smith <jeshuas@nvidia.com> Cc: Jeff Brasen <jbrasen@nvidia.com> Cc: Girish Mahadevan <gmahadevan@nvidia.com> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
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@ -33,6 +33,7 @@ typedef enum ArchCommonObjectID {
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EArchCommonObjPciInterruptMapInfo, ///< 10 - Pci Interrupt Map Info
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EArchCommonObjMemoryAffinityInfo, ///< 11 - Memory Affinity Info
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EArchCommonObjDeviceHandleAcpi, ///< 12 - Device Handle Acpi
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EArchCommonObjDeviceHandlePci, ///< 13 - Device Handle Pci
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EArchCommonObjMax
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} EARCH_COMMON_OBJECT_ID;
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@ -256,6 +257,25 @@ typedef struct CmArchCommonDeviceHandleAcpi {
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UINT32 Uid;
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} CM_ARCH_COMMON_DEVICE_HANDLE_ACPI;
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/** A structure that describes the PCI Device Handle (Type 1) in the
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Generic Initiator Affinity structure in SRAT
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ID: EArchCommonObjDeviceHandlePci
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*/
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typedef struct CmArchCommonDeviceHandlePci {
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/// PCI Segment Number
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UINT16 SegmentNumber;
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/// PCI Bus Number - Max 256 busses (Bits 15:8 of BDF)
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UINT8 BusNumber;
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/// PCI Device Number - Max 32 devices (Bits 7:3 of BDF)
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UINT8 DeviceNumber;
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/// PCI Function Number - Max 8 functions (Bits 2:0 of BDF)
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UINT8 FunctionNumber;
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} CM_ARCH_COMMON_DEVICE_HANDLE_PCI;
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#pragma pack()
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#endif // ARCH_COMMON_NAMESPACE_OBJECTS_H_
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@ -50,21 +50,20 @@ typedef enum ArmObjectID {
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EArmObjSmmuInterruptArray, ///< 19 - SMMU Interrupt Array
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EArmObjProcHierarchyInfo, ///< 20 - Processor Hierarchy Info
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EArmObjCacheInfo, ///< 21 - Cache Info
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EArmObjDeviceHandlePci, ///< 22 - Device Handle Pci
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EArmObjGenericInitiatorAffinityInfo, ///< 23 - Generic Initiator Affinity
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EArmObjCmn600Info, ///< 24 - CMN-600 Info
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EArmObjLpiInfo, ///< 25 - Lpi Info
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EArmObjRmr, ///< 26 - Reserved Memory Range Node
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EArmObjMemoryRangeDescriptor, ///< 27 - Memory Range Descriptor
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EArmObjCpcInfo, ///< 28 - Continuous Performance Control Info
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EArmObjPccSubspaceType0Info, ///< 29 - Pcc Subspace Type 0 Info
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EArmObjPccSubspaceType1Info, ///< 30 - Pcc Subspace Type 2 Info
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EArmObjPccSubspaceType2Info, ///< 31 - Pcc Subspace Type 2 Info
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EArmObjPccSubspaceType3Info, ///< 32 - Pcc Subspace Type 3 Info
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EArmObjPccSubspaceType4Info, ///< 33 - Pcc Subspace Type 4 Info
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EArmObjPccSubspaceType5Info, ///< 34 - Pcc Subspace Type 5 Info
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EArmObjEtInfo, ///< 35 - Embedded Trace Extension/Module Info
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EArmObjPsdInfo, ///< 36 - P-State Dependency (PSD) Info
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EArmObjGenericInitiatorAffinityInfo, ///< 22 - Generic Initiator Affinity
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EArmObjCmn600Info, ///< 23 - CMN-600 Info
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EArmObjLpiInfo, ///< 24 - Lpi Info
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EArmObjRmr, ///< 25 - Reserved Memory Range Node
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EArmObjMemoryRangeDescriptor, ///< 26 - Memory Range Descriptor
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EArmObjCpcInfo, ///< 27 - Continuous Performance Control Info
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EArmObjPccSubspaceType0Info, ///< 28 - Pcc Subspace Type 0 Info
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EArmObjPccSubspaceType1Info, ///< 29 - Pcc Subspace Type 2 Info
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EArmObjPccSubspaceType2Info, ///< 30 - Pcc Subspace Type 2 Info
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EArmObjPccSubspaceType3Info, ///< 31 - Pcc Subspace Type 3 Info
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EArmObjPccSubspaceType4Info, ///< 32 - Pcc Subspace Type 4 Info
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EArmObjPccSubspaceType5Info, ///< 33 - Pcc Subspace Type 5 Info
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EArmObjEtInfo, ///< 34 - Embedded Trace Extension/Module Info
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EArmObjPsdInfo, ///< 35 - P-State Dependency (PSD) Info
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EArmObjMax
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} EARM_OBJECT_ID;
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@ -719,25 +718,6 @@ typedef struct CmArmCacheInfo {
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UINT32 CacheId;
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} CM_ARM_CACHE_INFO;
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/** A structure that describes the PCI Device Handle (Type 1) in the
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Generic Initiator Affinity structure in SRAT
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ID: EArmObjDeviceHandlePci
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*/
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typedef struct CmArmDeviceHandlePci {
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/// PCI Segment Number
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UINT16 SegmentNumber;
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/// PCI Bus Number - Max 256 busses (Bits 15:8 of BDF)
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UINT8 BusNumber;
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/// PCI Device Number - Max 32 devices (Bits 7:3 of BDF)
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UINT8 DeviceNumber;
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/// PCI Function Number - Max 8 functions (Bits 2:0 of BDF)
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UINT8 FunctionNumber;
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} CM_ARM_DEVICE_HANDLE_PCI;
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/** A structure that describes the Generic Initiator Affinity structure in SRAT
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ID: EArmObjGenericInitiatorAffinityInfo
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@ -35,7 +35,7 @@
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- EArchCommonObjMemoryAffinityInfo (OPTIONAL)
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- EArmObjGenericInitiatorAffinityInfo (OPTIONAL)
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- EArchCommonObjDeviceHandleAcpi (OPTIONAL)
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- EArmObjDeviceHandlePci (OPTIONAL)
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- EArchCommonObjDeviceHandlePci (OPTIONAL)
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*/
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/** This macro expands to a function that retrieves the GIC
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@ -92,9 +92,9 @@ GET_OBJECT_LIST (
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information from the Configuration Manager.
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*/
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GET_OBJECT_LIST (
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EObjNameSpaceArm,
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EArmObjDeviceHandlePci,
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CM_ARM_DEVICE_HANDLE_PCI
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EObjNameSpaceArchCommon,
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EArchCommonObjDeviceHandlePci,
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CM_ARCH_COMMON_DEVICE_HANDLE_PCI
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);
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/** Return the PCI Device information in BDF format
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@ -110,7 +110,7 @@ GET_OBJECT_LIST (
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STATIC
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UINT16
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GetBdf (
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IN CONST CM_ARM_DEVICE_HANDLE_PCI *DeviceHandlePci
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IN CONST CM_ARCH_COMMON_DEVICE_HANDLE_PCI *DeviceHandlePci
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)
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{
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UINT16 Bdf;
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@ -302,7 +302,7 @@ AddGenericInitiatorAffinity (
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EFI_STATUS Status;
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EFI_ACPI_6_3_GENERIC_INITIATOR_AFFINITY_STRUCTURE *GenInitAff;
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CM_ARCH_COMMON_DEVICE_HANDLE_ACPI *DeviceHandleAcpi;
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CM_ARM_DEVICE_HANDLE_PCI *DeviceHandlePci;
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CM_ARCH_COMMON_DEVICE_HANDLE_PCI *DeviceHandlePci;
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UINT32 DeviceHandleCount;
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ASSERT (Srat != NULL);
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@ -362,7 +362,7 @@ AddGenericInitiatorAffinity (
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} else if (GenInitAffInfo->DeviceHandleType ==
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EFI_ACPI_6_3_PCI_DEVICE_HANDLE)
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{
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Status = GetEArmObjDeviceHandlePci (
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Status = GetEArchCommonObjDeviceHandlePci (
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CfgMgrProtocol,
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GenInitAffInfo->DeviceHandleToken,
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&DeviceHandlePci,
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@ -165,21 +165,20 @@ CM_OBJECT_TOKEN_FIXER TokenFixer[EArmObjMax] = {
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NULL, ///< 19 - SMMU Interrupt Array
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TokenFixerNotImplemented, ///< 20 - Processor Hierarchy Info
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TokenFixerNotImplemented, ///< 21 - Cache Info
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NULL, ///< 22 - Device Handle Pci
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NULL, ///< 23 - Generic Initiator Affinity
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NULL, ///< 24 - CMN-600 Info
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NULL, ///< 25 - Lpi Info
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NULL, ///< 26 - Reserved Memory Range Node
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NULL, ///< 27 - Memory Range Descriptor
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NULL, ///< 28 - Continuous Performance Control Info
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NULL, ///< 29 - Pcc Subspace Type 0 Info
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NULL, ///< 22 - Generic Initiator Affinity
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NULL, ///< 23 - CMN-600 Info
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NULL, ///< 24 - Lpi Info
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NULL, ///< 25 - Reserved Memory Range Node
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NULL, ///< 26 - Memory Range Descriptor
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NULL, ///< 27 - Continuous Performance Control Info
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NULL, ///< 28 - Pcc Subspace Type 0 Info
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NULL, ///< 29 - Pcc Subspace Type 2 Info
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NULL, ///< 30 - Pcc Subspace Type 2 Info
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NULL, ///< 31 - Pcc Subspace Type 2 Info
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NULL, ///< 32 - Pcc Subspace Type 3 Info
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NULL, ///< 33 - Pcc Subspace Type 4 Info
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NULL, ///< 34 - Pcc Subspace Type 5 Info
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NULL, ///< 35 - Embedded Trace Extension/Module Info
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NULL ///< 36 - P-State Dependency (PSD) Info
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NULL, ///< 31 - Pcc Subspace Type 3 Info
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NULL, ///< 32 - Pcc Subspace Type 4 Info
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NULL, ///< 33 - Pcc Subspace Type 5 Info
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NULL, ///< 34 - Embedded Trace Extension/Module Info
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NULL ///< 35 - P-State Dependency (PSD) Info
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};
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/** CmObj token fixer.
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@ -372,9 +372,9 @@ STATIC CONST CM_OBJ_PARSER CmArchCommonDeviceHandleAcpiParser[] = {
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{ "Uid", 4, "0x%x", NULL }
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};
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/** A parser for EArmObjDeviceHandlePci.
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/** A parser for EArchCommonObjDeviceHandlePci.
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*/
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STATIC CONST CM_OBJ_PARSER CmArmDeviceHandlePciParser[] = {
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STATIC CONST CM_OBJ_PARSER CmArchCommonDeviceHandlePciParser[] = {
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{ "SegmentNumber", 2, "0x%x", NULL },
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{ "BusNumber", 1, "0x%x", NULL },
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{ "DeviceNumber", 1, "0x%x", NULL },
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@ -683,6 +683,7 @@ STATIC CONST CM_OBJ_PARSER_ARRAY ArchCommonNamespaceObjectParser[] = {
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CM_PARSER_ADD_OBJECT (EArchCommonObjPciInterruptMapInfo, CmArchCommonPciInterruptMapInfoParser),
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CM_PARSER_ADD_OBJECT (EArchCommonObjMemoryAffinityInfo, CmArchCommonMemoryAffinityInfoParser),
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CM_PARSER_ADD_OBJECT (EArchCommonObjDeviceHandleAcpi, CmArchCommonDeviceHandleAcpiParser),
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CM_PARSER_ADD_OBJECT (EArchCommonObjDeviceHandlePci, CmArchCommonDeviceHandlePciParser),
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CM_PARSER_ADD_OBJECT_RESERVED (EArchCommonObjMax)
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};
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@ -711,7 +712,6 @@ STATIC CONST CM_OBJ_PARSER_ARRAY ArmNamespaceObjectParser[] = {
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CM_PARSER_ADD_OBJECT (EArmObjSmmuInterruptArray, CmArchCommonGenericInterruptParser),
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CM_PARSER_ADD_OBJECT (EArmObjProcHierarchyInfo, CmArmProcHierarchyInfoParser),
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CM_PARSER_ADD_OBJECT (EArmObjCacheInfo, CmArmCacheInfoParser),
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CM_PARSER_ADD_OBJECT (EArmObjDeviceHandlePci, CmArmDeviceHandlePciParser),
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CM_PARSER_ADD_OBJECT (EArmObjGenericInitiatorAffinityInfo,CmArmGenericInitiatorAffinityInfoParser),
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CM_PARSER_ADD_OBJECT (EArmObjCmn600Info, CmArmCmn600InfoParser),
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CM_PARSER_ADD_OBJECT (EArmObjLpiInfo, CmArmLpiInfoParser),
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@ -462,21 +462,20 @@ The CM_OBJECT_ID type is used to identify the Configuration Manager
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| 19 | SMMU Interrupt Array | |
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| 20 | Processor Hierarchy Info | Move to Arch Common NS |
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| 21 | Cache Info | Move to Arch Common NS |
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| 22 | Device Handle PCI | Move to Arch Common NS |
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| 23 | Generic Initiator Affinity Info | Move to Arch Common NS |
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| 24 | CMN 600 Info | |
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| 25 | Low Power Idle State Info | Move to Arch Common NS |
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| 26 | Reserved Memory Range Node | |
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| 27 | Memory Range Descriptor | |
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| 28 | Continuous Performance Control Info | Move to Arch Common NS |
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| 29 | Pcc Subspace Type 0 Info | Move to Arch Common NS |
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| 30 | Pcc Subspace Type 1 Info | Move to Arch Common NS |
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| 31 | Pcc Subspace Type 2 Info | Move to Arch Common NS |
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| 32 | Pcc Subspace Type 3 Info | Move to Arch Common NS |
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| 33 | Pcc Subspace Type 4 Info | Move to Arch Common NS |
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| 34 | Pcc Subspace Type 5 Info | Move to Arch Common NS |
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| 35 | Embedded Trace Extension/Module Info | |
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| 36 | P-State Dependency (PSD) Info | Move to Arch Common NS |
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| 22 | Generic Initiator Affinity Info | Move to Arch Common NS |
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| 23 | CMN 600 Info | |
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| 24 | Low Power Idle State Info | Move to Arch Common NS |
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| 25 | Reserved Memory Range Node | |
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| 26 | Memory Range Descriptor | |
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| 27 | Continuous Performance Control Info | Move to Arch Common NS |
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| 28 | Pcc Subspace Type 0 Info | Move to Arch Common NS |
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| 29 | Pcc Subspace Type 1 Info | Move to Arch Common NS |
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| 30 | Pcc Subspace Type 2 Info | Move to Arch Common NS |
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| 31 | Pcc Subspace Type 3 Info | Move to Arch Common NS |
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| 32 | Pcc Subspace Type 4 Info | Move to Arch Common NS |
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| 33 | Pcc Subspace Type 5 Info | Move to Arch Common NS |
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| 34 | Embedded Trace Extension/Module Info | |
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| 35 | P-State Dependency (PSD) Info | Move to Arch Common NS |
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| `*` | All other values are reserved. | |
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#### Object ID's in the Arch Common Namespace:
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@ -496,4 +495,5 @@ The CM_OBJECT_ID type is used to identify the Configuration Manager
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| 10 | PCI Interrupt Map Info | |
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| 11 | Memory Affinity Info | |
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| 12 | Device Handle Acpi | |
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| 13 | Device Handle PCI | |
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| `*` | All other values are reserved. | |
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