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ArmPkg: ArmLib: purge incorrect ArmDrainWriteBuffer () alias 

In ArmLib, there exists an alias for ArmDataSynchronizationBarrier,
named after one of several names for the pre-ARMv6 cp15 operation that
was formalised into the Data Synchronization Barrier in ARMv6.

This alias is also the one called from within ArmLib, in preference of
the correct name. Through the power of code reuse, this name slipped
into the AArch64 variant as well.

Expunge it from the codebase.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18915 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Leif Lindholm 2015-11-20 13:14:59 +00:00 committed by leiflindholm
parent f73dd6f5bb
commit 3b1495156a
6 changed files with 8 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
ArmPkg/Include/Library/ArmLib.h
View File

@ -391,12 +391,6 @@ ArmSetHighVectors (
VOID
);
VOID
EFIAPI
ArmDrainWriteBuffer (
VOID
);
VOID
EFIAPI
ArmDataMemoryBarrier (

8
ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c
View File

@ -33,7 +33,7 @@ AArch64DataCacheOperation (
AArch64AllDataCachesOperation (DataCacheOperation);
ArmDrainWriteBuffer ();
ArmDataSynchronizationBarrier ();
if (SavedInterruptState) {
ArmEnableInterrupts ();
@ -46,7 +46,7 @@ ArmInvalidateDataCache (
VOID
)
{
ArmDrainWriteBuffer ();
ArmDataSynchronizationBarrier ();
AArch64DataCacheOperation (ArmInvalidateDataCacheEntryBySetWay);
}
@ -56,7 +56,7 @@ ArmCleanInvalidateDataCache (
VOID
)
{
ArmDrainWriteBuffer ();
ArmDataSynchronizationBarrier ();
AArch64DataCacheOperation (ArmCleanInvalidateDataCacheEntryBySetWay);
}
@ -66,6 +66,6 @@ ArmCleanDataCache (
VOID
)
{
ArmDrainWriteBuffer ();
ArmDataSynchronizationBarrier ();
AArch64DataCacheOperation (ArmCleanDataCacheEntryBySetWay);
}

2
ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
View File

@ -26,7 +26,6 @@ GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA)
GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay)
GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay)
GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryBySetWay)
GCC_ASM_EXPORT (ArmDrainWriteBuffer)
GCC_ASM_EXPORT (ArmEnableMmu)
GCC_ASM_EXPORT (ArmDisableMmu)
GCC_ASM_EXPORT (ArmDisableCachesAndMmu)
@ -364,7 +363,6 @@ ASM_PFX(ArmDataMemoryBarrier):
ASM_PFX(ArmDataSynchronizationBarrier):
ASM_PFX(ArmDrainWriteBuffer):
dsb sy
ret

8
ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.c
View File

@ -32,7 +32,7 @@ ArmV7DataCacheOperation (
ArmV7AllDataCachesOperation (DataCacheOperation);
ArmDrainWriteBuffer ();
ArmDataSynchronizationBarrier ();
if (SavedInterruptState) {
ArmEnableInterrupts ();
@ -45,7 +45,7 @@ ArmInvalidateDataCache (
VOID
)
{
ArmDrainWriteBuffer ();
ArmDataSynchronizationBarrier ();
ArmV7DataCacheOperation (ArmInvalidateDataCacheEntryBySetWay);
}
@ -55,7 +55,7 @@ ArmCleanInvalidateDataCache (
VOID
)
{
ArmDrainWriteBuffer ();
ArmDataSynchronizationBarrier ();
ArmV7DataCacheOperation (ArmCleanInvalidateDataCacheEntryBySetWay);
}
@ -65,6 +65,6 @@ ArmCleanDataCache (
VOID
)
{
ArmDrainWriteBuffer ();
ArmDataSynchronizationBarrier ();
ArmV7DataCacheOperation (ArmCleanDataCacheEntryBySetWay);
}

2
ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
View File

@ -23,7 +23,6 @@ GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA)
GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay)
GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay)
GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryBySetWay)
GCC_ASM_EXPORT (ArmDrainWriteBuffer)
GCC_ASM_EXPORT (ArmEnableMmu)
GCC_ASM_EXPORT (ArmDisableMmu)
GCC_ASM_EXPORT (ArmDisableCachesAndMmu)
@ -261,7 +260,6 @@ ASM_PFX(ArmDataMemoryBarrier):
bx LR
ASM_PFX(ArmDataSynchronizationBarrier):
ASM_PFX(ArmDrainWriteBuffer):
dsb
bx LR

2
ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
View File

@ -20,7 +20,6 @@
EXPORT ArmInvalidateDataCacheEntryBySetWay
EXPORT ArmCleanDataCacheEntryBySetWay
EXPORT ArmCleanInvalidateDataCacheEntryBySetWay
EXPORT ArmDrainWriteBuffer
EXPORT ArmEnableMmu
EXPORT ArmDisableMmu
EXPORT ArmDisableCachesAndMmu
@ -255,7 +254,6 @@ ArmDataMemoryBarrier
bx LR
ArmDataSynchronizationBarrier
ArmDrainWriteBuffer
dsb
bx LR