mirror of https://github.com/acidanthera/audk.git
OvmfPkg/ResetVector: Save the encryption mask at boot time
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3108 The early assembler code performs validation for some of the SEV-related information, specifically the encryption bit position. To avoid having to re-validate the encryption bit position as the system proceeds through its boot phases, save the validated encryption bit position in the SEV-ES work area for use by later phases. Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ard Biesheuvel <ard.biesheuvel@arm.com> Cc: Brijesh Singh <brijesh.singh@amd.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Message-Id: <2609724859cf21f0c6d45bc323e94465dca4e621.1610045305.git.thomas.lendacky@amd.com>
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@ -29,6 +29,8 @@ typedef struct _SEC_SEV_ES_WORK_AREA {
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UINT8 Reserved1[7];
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UINT64 RandomData;
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UINT64 EncryptionMask;
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} SEC_SEV_ES_WORK_AREA;
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/**
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@ -145,7 +145,7 @@ GetSevEncBit:
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; The encryption bit position is always above 31
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sub ebx, 32
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jns SevExit
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jns SevSaveMask
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; Encryption bit was reported as 31 or below, enter a HLT loop
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SevEncBitLowHlt:
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@ -153,6 +153,14 @@ SevEncBitLowHlt:
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hlt
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jmp SevEncBitLowHlt
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SevSaveMask:
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xor edx, edx
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bts edx, ebx
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mov dword[SEV_ES_WORK_AREA_ENC_MASK], 0
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mov dword[SEV_ES_WORK_AREA_ENC_MASK + 4], edx
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jmp SevExit
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NoSev:
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;
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; Perform an SEV-ES sanity check by seeing if a #VC exception occurred.
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@ -74,6 +74,7 @@
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%define GHCB_SIZE (FixedPcdGet32 (PcdOvmfSecGhcbSize))
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%define SEV_ES_WORK_AREA (FixedPcdGet32 (PcdSevEsWorkAreaBase))
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%define SEV_ES_WORK_AREA_RDRAND (FixedPcdGet32 (PcdSevEsWorkAreaBase) + 8)
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%define SEV_ES_WORK_AREA_ENC_MASK (FixedPcdGet32 (PcdSevEsWorkAreaBase) + 16)
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%define SEV_ES_VC_TOP_OF_STACK (FixedPcdGet32 (PcdOvmfSecPeiTempRamBase) + FixedPcdGet32 (PcdOvmfSecPeiTempRamSize))
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%include "Ia32/Flat32ToFlat64.asm"
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%include "Ia32/PageTables64.asm"
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