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ArmPkg/ArmMmuLib ARM: Split off XN page descriptor bit from type field

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With large page support out of the picture, we can treat bits 1 and 0 of
the page descriptor as individual valid and XN bits, instead of treating
XN as a page type. Doing so aligns the handling of the attribute with
the section descriptor layout, as well as the XN handling on AArch64,
and this is beneficial for maintainability.

Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
This commit is contained in:
Ard Biesheuvel 2023-02-09 10:01:45 +01:00 committed by mergify[bot]
parent 82ccaaf8e7
commit 3b76284883
2 changed files with 9 additions and 11 deletions
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8
ArmPkg/Include/Chipset/ArmV7Mmu.h
View File

@ -54,11 +54,9 @@
#define TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(Desc) (((Desc) & 3UL) == TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE) #define TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(Desc) (((Desc) & 3UL) == TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE)
// Translation table descriptor types // Translation table descriptor types
#define TT_DESCRIPTOR_PAGE_TYPE_MASK (3UL << 0) #define TT_DESCRIPTOR_PAGE_TYPE_MASK (1UL << 1)
#define TT_DESCRIPTOR_PAGE_TYPE_FAULT (0UL << 0) #define TT_DESCRIPTOR_PAGE_TYPE_FAULT (0UL << 1)
#define TT_DESCRIPTOR_PAGE_TYPE_PAGE (2UL << 0) #define TT_DESCRIPTOR_PAGE_TYPE_PAGE (1UL << 1)
#define TT_DESCRIPTOR_PAGE_TYPE_PAGE_XN (3UL << 0)
#define TT_DESCRIPTOR_PAGE_TYPE_LARGEPAGE (1UL << 0)
// Section descriptor definitions // Section descriptor definitions
#define TT_DESCRIPTOR_SECTION_SIZE (0x00100000) #define TT_DESCRIPTOR_SECTION_SIZE (0x00100000)

12
ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c
View File

@ -104,12 +104,8 @@ UpdatePageEntries (
// EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone) // EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)
// EntryValue: values at bit positions specified by EntryMask // EntryValue: values at bit positions specified by EntryMask
EntryMask = TT_DESCRIPTOR_PAGE_TYPE_MASK | TT_DESCRIPTOR_PAGE_AP_MASK; EntryMask = TT_DESCRIPTOR_PAGE_TYPE_MASK | TT_DESCRIPTOR_PAGE_AP_MASK | TT_DESCRIPTOR_PAGE_XN_MASK;
if ((Attributes & EFI_MEMORY_XP) != 0) { EntryValue = TT_DESCRIPTOR_PAGE_TYPE_PAGE;
EntryValue = TT_DESCRIPTOR_PAGE_TYPE_PAGE_XN;
} else {
EntryValue = TT_DESCRIPTOR_PAGE_TYPE_PAGE;
}
// Although the PI spec is unclear on this, the GCD guarantees that only // Although the PI spec is unclear on this, the GCD guarantees that only
// one Attribute bit is set at a time, so the order of the conditionals below // one Attribute bit is set at a time, so the order of the conditionals below
@ -148,6 +144,10 @@ UpdatePageEntries (
EntryValue |= TT_DESCRIPTOR_PAGE_AP_RW_RW; EntryValue |= TT_DESCRIPTOR_PAGE_AP_RW_RW;
} }
if ((Attributes & EFI_MEMORY_XP) != 0) {
EntryValue |= TT_DESCRIPTOR_PAGE_XN_MASK;
}
// Obtain page table base // Obtain page table base
FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress (); FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();