mirror of https://github.com/acidanthera/audk.git
PcAtChipsetPkg/PciHostBridgeDxe/PciRootBridgeIo.c: rewrap code, strip trailing ws
In this patch the code and the comments embedded in code are rewrapped to 79 columns, plus any trailing whitespace is stripped. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Regression-tested-by: Gabriel Somlo <somlo@cmu.edu> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17950 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Laszlo Ersek
lersek
parent
5c1d397dc2
commit
3cb4bb68e9
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@ -22,7 +22,7 @@ typedef struct {
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RESOURCE_CONFIGURATION Configuration = {
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{{0x8A, 0x2B, 1, 0, 0, 0, 0, 0, 0, 0},
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{0x8A, 0x2B, 0, 0, 0, 32, 0, 0, 0, 0},
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{0x8A, 0x2B, 0, 0, 0, 32, 0, 0, 0, 0},
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{0x8A, 0x2B, 0, 0, 6, 32, 0, 0, 0, 0},
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{0x8A, 0x2B, 0, 0, 0, 64, 0, 0, 0, 0},
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{0x8A, 0x2B, 0, 0, 6, 64, 0, 0, 0, 0},
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@ -80,7 +80,7 @@ RESOURCE_CONFIGURATION Configuration = {
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**/
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EFI_STATUS
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EFIAPI
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RootBridgeIoPollMem (
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RootBridgeIoPollMem (
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
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IN UINT64 Address,
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@ -135,7 +135,7 @@ RootBridgeIoPollMem (
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**/
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EFI_STATUS
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EFIAPI
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RootBridgeIoPollIo (
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RootBridgeIoPollIo (
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
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IN UINT64 Address,
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@ -723,8 +723,8 @@ RootBridgeIoSetAttributes (
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
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IN UINT64 Attributes,
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IN OUT UINT64 *ResourceBase,
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IN OUT UINT64 *ResourceLength
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);
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IN OUT UINT64 *ResourceLength
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);
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/**
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Retrieves the current resource settings of this PCI root bridge in the form
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@ -851,7 +851,7 @@ RootBridgeConstructor (
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//
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PrivateData->BusBase = ResAperture->BusBase;
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PrivateData->BusLimit = ResAperture->BusLimit;
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//
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// Specific for this chipset
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//
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@ -861,17 +861,20 @@ RootBridgeConstructor (
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PrivateData->ResAllocNode[Index].Length = 0;
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PrivateData->ResAllocNode[Index].Status = ResNone;
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}
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PrivateData->RootBridgeAttrib = Attri;
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PrivateData->Supports = EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO | EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO | \
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EFI_PCI_ATTRIBUTE_ISA_IO_16 | EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO | \
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EFI_PCI_ATTRIBUTE_VGA_MEMORY | \
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EFI_PCI_ATTRIBUTE_VGA_IO_16 | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;
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PrivateData->Supports = EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO |
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EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO |
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EFI_PCI_ATTRIBUTE_ISA_IO_16 |
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EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO |
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EFI_PCI_ATTRIBUTE_VGA_MEMORY |
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EFI_PCI_ATTRIBUTE_VGA_IO_16 |
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EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;
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PrivateData->Attributes = PrivateData->Supports;
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Protocol->ParentHandle = HostBridgeHandle;
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Protocol->PollMem = RootBridgeIoPollMem;
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Protocol->PollIo = RootBridgeIoPollIo;
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@ -901,7 +904,8 @@ RootBridgeConstructor (
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Protocol->SegmentNumber = 0;
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Status = gBS->LocateProtocol (&gEfiMetronomeArchProtocolGuid, NULL, (VOID **)&mMetronome);
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Status = gBS->LocateProtocol (&gEfiMetronomeArchProtocolGuid, NULL,
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(VOID **)&mMetronome);
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ASSERT_EFI_ERROR (Status);
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return EFI_SUCCESS;
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@ -1001,18 +1005,18 @@ RootBridgeIoCheckParameter (
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PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);
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//
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// Check to see if any address associated with this transfer exceeds the maximum
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// allowed address. The maximum address implied by the parameters passed in is
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// Address + Size * Count. If the following condition is met, then the transfer
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// is not supported.
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// Check to see if any address associated with this transfer exceeds the
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// maximum allowed address. The maximum address implied by the parameters
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// passed in is Address + Size * Count. If the following condition is met,
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// then the transfer is not supported.
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//
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// Address + Size * Count > Limit + 1
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//
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// Since Limit can be the maximum integer value supported by the CPU and Count
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// can also be the maximum integer value supported by the CPU, this range
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// check must be adjusted to avoid all oveflow conditions.
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//
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// The following form of the range check is equivalent but assumes that
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// Since Limit can be the maximum integer value supported by the CPU and
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// Count can also be the maximum integer value supported by the CPU, this
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// range check must be adjusted to avoid all oveflow conditions.
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//
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// The following form of the range check is equivalent but assumes that
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// Limit is of the form (2^n - 1).
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//
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if (OperationType == IoOperation) {
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@ -1023,11 +1027,13 @@ RootBridgeIoCheckParameter (
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Limit = PrivateData->MemLimit;
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} else {
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PciRbAddr = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &Address;
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if (PciRbAddr->Bus < PrivateData->BusBase || PciRbAddr->Bus > PrivateData->BusLimit) {
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if (PciRbAddr->Bus < PrivateData->BusBase ||
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PciRbAddr->Bus > PrivateData->BusLimit) {
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return EFI_INVALID_PARAMETER;
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}
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if (PciRbAddr->Device > MAX_PCI_DEVICE_NUMBER || PciRbAddr->Function > MAX_PCI_FUNCTION_NUMBER) {
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if (PciRbAddr->Device > MAX_PCI_DEVICE_NUMBER ||
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PciRbAddr->Function > MAX_PCI_FUNCTION_NUMBER) {
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return EFI_INVALID_PARAMETER;
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}
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@ -1048,7 +1054,7 @@ RootBridgeIoCheckParameter (
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if (Address > Limit) {
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return EFI_UNSUPPORTED;
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}
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} else {
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} else {
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MaxCount = RShiftU64 (Limit, Width);
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if (MaxCount < (Count - 1)) {
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return EFI_UNSUPPORTED;
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@ -1107,7 +1113,8 @@ RootBridgeIoMemRW (
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EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth;
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UINT8 *Uint8Buffer;
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Status = RootBridgeIoCheckParameter (This, MemOperation, Width, Address, Count, Buffer);
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Status = RootBridgeIoCheckParameter (This, MemOperation, Width, Address,
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Count, Buffer);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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@ -1115,7 +1122,9 @@ RootBridgeIoMemRW (
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InStride = mInStride[Width];
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OutStride = mOutStride[Width];
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OperationWidth = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);
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for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
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for (Uint8Buffer = Buffer;
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Count > 0;
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Address += InStride, Uint8Buffer += OutStride, Count--) {
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if (Write) {
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switch (OperationWidth) {
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case EfiPciWidthUint8:
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@ -1162,7 +1171,7 @@ RootBridgeIoMemRW (
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}
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}
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}
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return EFI_SUCCESS;
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return EFI_SUCCESS;
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}
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/**
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@ -1212,7 +1221,8 @@ RootBridgeIoIoRW (
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EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth;
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UINT8 *Uint8Buffer;
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Status = RootBridgeIoCheckParameter (This, IoOperation, Width, Address, Count, Buffer);
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Status = RootBridgeIoCheckParameter (This, IoOperation, Width, Address,
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Count, Buffer);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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@ -1265,7 +1275,9 @@ RootBridgeIoIoRW (
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}
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#endif
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for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
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for (Uint8Buffer = Buffer;
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Count > 0;
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Address += InStride, Uint8Buffer += OutStride, Count--) {
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if (Write) {
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switch (OperationWidth) {
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case EfiPciWidthUint8:
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@ -1358,7 +1370,8 @@ RootBridgeIoPciRW (
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EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *PciRbAddr;
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UINTN PcieRegAddr;
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Status = RootBridgeIoCheckParameter (This, PciOperation, Width, Address, Count, Buffer);
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Status = RootBridgeIoCheckParameter (This, PciOperation, Width, Address,
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Count, Buffer);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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@ -1377,7 +1390,9 @@ RootBridgeIoPciRW (
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InStride = mInStride[Width];
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OutStride = mOutStride[Width];
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OperationWidth = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);
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for (Uint8Buffer = Buffer; Count > 0; PcieRegAddr += InStride, Uint8Buffer += OutStride, Count--) {
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for (Uint8Buffer = Buffer;
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Count > 0;
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PcieRegAddr += InStride, Uint8Buffer += OutStride, Count--) {
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if (Write) {
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switch (OperationWidth) {
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case EfiPciWidthUint8:
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@ -1468,7 +1483,7 @@ RootBridgeIoPciRW (
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**/
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EFI_STATUS
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EFIAPI
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RootBridgeIoPollMem (
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RootBridgeIoPollMem (
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
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IN UINT64 Address,
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@ -1496,40 +1511,42 @@ RootBridgeIoPollMem (
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Status = This->Mem.Read (This, Width, Address, 1, Result);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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}
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if ((*Result & Mask) == Value) {
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return EFI_SUCCESS;
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}
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if (Delay == 0) {
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return EFI_SUCCESS;
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} else {
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//
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// Determine the proper # of metronome ticks to wait for polling the
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// location. The nuber of ticks is Roundup (Delay / mMetronome->TickPeriod)+1
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// location. The nuber of ticks is Roundup (Delay /
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// mMetronome->TickPeriod)+1
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// The "+1" to account for the possibility of the first tick being short
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// because we started in the middle of a tick.
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//
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// BugBug: overriding mMetronome->TickPeriod with UINT32 until Metronome
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// protocol definition is updated.
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//
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NumberOfTicks = DivU64x32Remainder (Delay, (UINT32) mMetronome->TickPeriod, &Remainder);
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NumberOfTicks = DivU64x32Remainder (Delay, (UINT32) mMetronome->TickPeriod,
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&Remainder);
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if (Remainder != 0) {
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NumberOfTicks += 1;
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}
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NumberOfTicks += 1;
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while (NumberOfTicks != 0) {
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mMetronome->WaitForTick (mMetronome, 1);
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Status = This->Mem.Read (This, Width, Address, 1, Result);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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if ((*Result & Mask) == Value) {
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return EFI_SUCCESS;
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}
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@ -1584,7 +1601,7 @@ RootBridgeIoPollMem (
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**/
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EFI_STATUS
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EFIAPI
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RootBridgeIoPollIo (
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RootBridgeIoPollIo (
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
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IN UINT64 Address,
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@ -1609,41 +1626,43 @@ RootBridgeIoPollIo (
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if ((UINT32)Width > EfiPciWidthUint64) {
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return EFI_INVALID_PARAMETER;
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}
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Status = This->Io.Read (This, Width, Address, 1, Result);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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}
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if ((*Result & Mask) == Value) {
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return EFI_SUCCESS;
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}
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if (Delay == 0) {
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return EFI_SUCCESS;
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} else {
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//
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// Determine the proper # of metronome ticks to wait for polling the
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// location. The number of ticks is Roundup (Delay / mMetronome->TickPeriod)+1
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// location. The number of ticks is Roundup (Delay /
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// mMetronome->TickPeriod)+1
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// The "+1" to account for the possibility of the first tick being short
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// because we started in the middle of a tick.
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//
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NumberOfTicks = DivU64x32Remainder (Delay, (UINT32)mMetronome->TickPeriod, &Remainder);
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NumberOfTicks = DivU64x32Remainder (Delay, (UINT32)mMetronome->TickPeriod,
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&Remainder);
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if (Remainder != 0) {
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NumberOfTicks += 1;
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}
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NumberOfTicks += 1;
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while (NumberOfTicks != 0) {
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mMetronome->WaitForTick (mMetronome, 1);
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Status = This->Io.Read (This, Width, Address, 1, Result);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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if ((*Result & Mask) == Value) {
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return EFI_SUCCESS;
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}
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@ -1745,7 +1764,7 @@ RootBridgeIoMemWrite (
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IN VOID *Buffer
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)
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{
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return RootBridgeIoMemRW (This, TRUE, Width, Address, Count, Buffer);
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return RootBridgeIoMemRW (This, TRUE, Width, Address, Count, Buffer);
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}
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/**
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@ -1787,7 +1806,7 @@ RootBridgeIoIoRead (
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OUT VOID *Buffer
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)
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{
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return RootBridgeIoIoRW (This, FALSE, Width, Address, Count, Buffer);
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return RootBridgeIoIoRW (This, FALSE, Width, Address, Count, Buffer);
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}
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/**
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@ -1828,7 +1847,7 @@ RootBridgeIoIoWrite (
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IN VOID *Buffer
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)
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{
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return RootBridgeIoIoRW (This, TRUE, Width, Address, Count, Buffer);
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return RootBridgeIoIoRW (This, TRUE, Width, Address, Count, Buffer);
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}
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/**
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@ -1886,7 +1905,7 @@ RootBridgeIoCopyMem (
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if ((UINT32)Width > EfiPciWidthUint64) {
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return EFI_INVALID_PARAMETER;
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}
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}
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if (DestAddress == SrcAddress) {
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return EFI_SUCCESS;
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@ -1895,7 +1914,8 @@ RootBridgeIoCopyMem (
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Stride = (UINTN)(1 << Width);
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Direction = TRUE;
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if ((DestAddress > SrcAddress) && (DestAddress < (SrcAddress + Count * Stride))) {
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if ((DestAddress > SrcAddress) &&
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(DestAddress < (SrcAddress + Count * Stride))) {
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Direction = FALSE;
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SrcAddress = SrcAddress + (Count-1) * Stride;
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DestAddress = DestAddress + (Count-1) * Stride;
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@ -2093,10 +2113,11 @@ RootBridgeIoMap (
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EFI_PHYSICAL_ADDRESS PhysicalAddress;
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MAP_INFO *MapInfo;
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if (HostAddress == NULL || NumberOfBytes == NULL || DeviceAddress == NULL || Mapping == NULL) {
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if (HostAddress == NULL || NumberOfBytes == NULL || DeviceAddress == NULL ||
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Mapping == NULL) {
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return EFI_INVALID_PARAMETER;
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}
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//
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// Initialize the return values to their defaults
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//
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@ -2119,10 +2140,11 @@ RootBridgeIoMap (
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//
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// Common Buffer operations can not be remapped. If the common buffer
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// if above 4GB, then it is not possible to generate a mapping, so return
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// if above 4GB, then it is not possible to generate a mapping, so return
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// an error.
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//
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if (Operation == EfiPciOperationBusMasterCommonBuffer || Operation == EfiPciOperationBusMasterCommonBuffer64) {
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if (Operation == EfiPciOperationBusMasterCommonBuffer ||
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Operation == EfiPciOperationBusMasterCommonBuffer64) {
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return EFI_UNSUPPORTED;
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}
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@ -2131,8 +2153,8 @@ RootBridgeIoMap (
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// called later.
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//
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Status = gBS->AllocatePool (
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EfiBootServicesData,
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sizeof(MAP_INFO),
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EfiBootServicesData,
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sizeof(MAP_INFO),
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(VOID **)&MapInfo
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);
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if (EFI_ERROR (Status)) {
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@ -2158,8 +2180,8 @@ RootBridgeIoMap (
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// Allocate a buffer below 4GB to map the transfer to.
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//
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Status = gBS->AllocatePages (
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AllocateMaxAddress,
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EfiBootServicesData,
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AllocateMaxAddress,
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EfiBootServicesData,
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MapInfo->NumberOfPages,
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&MapInfo->MappedHostAddress
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);
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@ -2174,9 +2196,10 @@ RootBridgeIoMap (
|
|||
// then copy the contents of the real buffer into the mapped buffer
|
||||
// so the Bus Master can read the contents of the real buffer.
|
||||
//
|
||||
if (Operation == EfiPciOperationBusMasterRead || Operation == EfiPciOperationBusMasterRead64) {
|
||||
if (Operation == EfiPciOperationBusMasterRead ||
|
||||
Operation == EfiPciOperationBusMasterRead64) {
|
||||
CopyMem (
|
||||
(VOID *)(UINTN)MapInfo->MappedHostAddress,
|
||||
(VOID *)(UINTN)MapInfo->MappedHostAddress,
|
||||
(VOID *)(UINTN)MapInfo->HostAddress,
|
||||
MapInfo->NumberOfBytes
|
||||
);
|
||||
|
|
@ -2188,7 +2211,8 @@ RootBridgeIoMap (
|
|||
*DeviceAddress = MapInfo->MappedHostAddress;
|
||||
} else {
|
||||
//
|
||||
// The transfer is below 4GB, so the DeviceAddress is simply the HostAddress
|
||||
// The transfer is below 4GB, so the DeviceAddress is simply the
|
||||
// HostAddress
|
||||
//
|
||||
*DeviceAddress = PhysicalAddress;
|
||||
}
|
||||
|
|
@ -2228,8 +2252,9 @@ RootBridgeIoUnmap (
|
|||
MAP_INFO *MapInfo;
|
||||
|
||||
//
|
||||
// See if the Map() operation associated with this Unmap() required a mapping buffer.
|
||||
// If a mapping buffer was not required, then this function simply returns EFI_SUCCESS.
|
||||
// See if the Map() operation associated with this Unmap() required a mapping
|
||||
// buffer. If a mapping buffer was not required, then this function simply
|
||||
// returns EFI_SUCCESS.
|
||||
//
|
||||
if (Mapping != NULL) {
|
||||
//
|
||||
|
|
@ -2242,9 +2267,10 @@ RootBridgeIoUnmap (
|
|||
// then copy the contents of the mapped buffer into the real buffer
|
||||
// so the processor can read the contents of the real buffer.
|
||||
//
|
||||
if (MapInfo->Operation == EfiPciOperationBusMasterWrite || MapInfo->Operation == EfiPciOperationBusMasterWrite64) {
|
||||
if (MapInfo->Operation == EfiPciOperationBusMasterWrite ||
|
||||
MapInfo->Operation == EfiPciOperationBusMasterWrite64) {
|
||||
CopyMem (
|
||||
(VOID *)(UINTN)MapInfo->HostAddress,
|
||||
(VOID *)(UINTN)MapInfo->HostAddress,
|
||||
(VOID *)(UINTN)MapInfo->MappedHostAddress,
|
||||
MapInfo->NumberOfBytes
|
||||
);
|
||||
|
|
@ -2321,11 +2347,13 @@ RootBridgeIoAllocateBuffer (
|
|||
if (HostAddress == NULL) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// The only valid memory types are EfiBootServicesData and EfiRuntimeServicesData
|
||||
// The only valid memory types are EfiBootServicesData and
|
||||
// EfiRuntimeServicesData
|
||||
//
|
||||
if (MemoryType != EfiBootServicesData && MemoryType != EfiRuntimeServicesData) {
|
||||
if (MemoryType != EfiBootServicesData &&
|
||||
MemoryType != EfiRuntimeServicesData) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
}
|
||||
|
||||
|
|
@ -2334,7 +2362,8 @@ RootBridgeIoAllocateBuffer (
|
|||
//
|
||||
PhysicalAddress = (EFI_PHYSICAL_ADDRESS)(0xffffffff);
|
||||
|
||||
Status = gBS->AllocatePages (AllocateMaxAddress, MemoryType, Pages, &PhysicalAddress);
|
||||
Status = gBS->AllocatePages (AllocateMaxAddress, MemoryType, Pages,
|
||||
&PhysicalAddress);
|
||||
if (EFI_ERROR (Status)) {
|
||||
return Status;
|
||||
}
|
||||
|
|
@ -2451,13 +2480,13 @@ RootBridgeIoGetAttributes (
|
|||
// Set the return value for Supported and Attributes
|
||||
//
|
||||
if (Supported != NULL) {
|
||||
*Supported = PrivateData->Supports;
|
||||
*Supported = PrivateData->Supports;
|
||||
}
|
||||
|
||||
if (Attributes != NULL) {
|
||||
*Attributes = PrivateData->Attributes;
|
||||
}
|
||||
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
|
|
@ -2510,23 +2539,23 @@ RootBridgeIoSetAttributes (
|
|||
IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
|
||||
IN UINT64 Attributes,
|
||||
IN OUT UINT64 *ResourceBase,
|
||||
IN OUT UINT64 *ResourceLength
|
||||
IN OUT UINT64 *ResourceLength
|
||||
)
|
||||
{
|
||||
PCI_ROOT_BRIDGE_INSTANCE *PrivateData;
|
||||
|
||||
|
||||
PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This);
|
||||
|
||||
|
||||
if (Attributes != 0) {
|
||||
if ((Attributes & (~(PrivateData->Supports))) != 0) {
|
||||
return EFI_UNSUPPORTED;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// This is a generic driver for a PC-AT class system. It does not have any
|
||||
// chipset specific knowlegde, so none of the attributes can be set or
|
||||
// cleared. Any attempt to set attribute that are already set will succeed,
|
||||
// chipset specific knowlegde, so none of the attributes can be set or
|
||||
// cleared. Any attempt to set attribute that are already set will succeed,
|
||||
// and any attempt to set an attribute that is not supported will fail.
|
||||
//
|
||||
if (Attributes & (~PrivateData->Attributes)) {
|
||||
|
|
@ -2578,16 +2607,20 @@ RootBridgeIoConfiguration (
|
|||
UINTN Index;
|
||||
|
||||
PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);
|
||||
|
||||
|
||||
for (Index = 0; Index < TypeMax; Index++) {
|
||||
if (PrivateData->ResAllocNode[Index].Status == ResAllocated) {
|
||||
Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->ResAllocNode[Index].Base;
|
||||
Configuration.SpaceDesp[Index].AddrRangeMax = PrivateData->ResAllocNode[Index].Base + PrivateData->ResAllocNode[Index].Length - 1;
|
||||
Configuration.SpaceDesp[Index].AddrLen = PrivateData->ResAllocNode[Index].Length;
|
||||
}
|
||||
}
|
||||
|
||||
*Resources = &Configuration;
|
||||
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Desc;
|
||||
|
||||
Desc = &Configuration.SpaceDesp[Index];
|
||||
Desc->AddrRangeMin = PrivateData->ResAllocNode[Index].Base;
|
||||
Desc->AddrRangeMax = PrivateData->ResAllocNode[Index].Base +
|
||||
PrivateData->ResAllocNode[Index].Length - 1;
|
||||
Desc->AddrLen = PrivateData->ResAllocNode[Index].Length;
|
||||
}
|
||||
}
|
||||
|
||||
*Resources = &Configuration;
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue