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PcAtChipsetPkg/PciHostBridgeDxe/PciRootBridgeIo.c: rewrap code, strip trailing ws 

In this patch the code and the comments embedded in code are rewrapped to
79 columns, plus any trailing whitespace is stripped.

Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Regression-tested-by: Gabriel Somlo <somlo@cmu.edu>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17950 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Laszlo Ersek 2015-07-14 12:01:30 +00:00 committed by lersek
parent 5c1d397dc2
commit 3cb4bb68e9
1 changed files with 123 additions and 90 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

109
PcAtChipsetPkg/PciHostBridgeDxe/PciRootBridgeIo.c
View File

@ -864,10 +864,13 @@ RootBridgeConstructor (
PrivateData->RootBridgeAttrib = Attri; PrivateData->RootBridgeAttrib = Attri;
PrivateData->Supports = EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO | EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO | \ PrivateData->Supports = EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO |
EFI_PCI_ATTRIBUTE_ISA_IO_16 | EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO | \ EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO |
EFI_PCI_ATTRIBUTE_VGA_MEMORY | \ EFI_PCI_ATTRIBUTE_ISA_IO_16 |
EFI_PCI_ATTRIBUTE_VGA_IO_16 | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16; EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO |
EFI_PCI_ATTRIBUTE_VGA_MEMORY |
EFI_PCI_ATTRIBUTE_VGA_IO_16 |
EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;
PrivateData->Attributes = PrivateData->Supports; PrivateData->Attributes = PrivateData->Supports;
Protocol->ParentHandle = HostBridgeHandle; Protocol->ParentHandle = HostBridgeHandle;
@ -901,7 +904,8 @@ RootBridgeConstructor (
Protocol->SegmentNumber = 0; Protocol->SegmentNumber = 0;
Status = gBS->LocateProtocol (&gEfiMetronomeArchProtocolGuid, NULL, (VOID **)&mMetronome); Status = gBS->LocateProtocol (&gEfiMetronomeArchProtocolGuid, NULL,
(VOID **)&mMetronome);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
return EFI_SUCCESS; return EFI_SUCCESS;
@ -1001,16 +1005,16 @@ RootBridgeIoCheckParameter (
PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This); PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);
// //
// Check to see if any address associated with this transfer exceeds the maximum // Check to see if any address associated with this transfer exceeds the
// allowed address. The maximum address implied by the parameters passed in is // maximum allowed address. The maximum address implied by the parameters
// Address + Size * Count. If the following condition is met, then the transfer // passed in is Address + Size * Count. If the following condition is met,
// is not supported. // then the transfer is not supported.
// //
// Address + Size * Count > Limit + 1 // Address + Size * Count > Limit + 1
// //
// Since Limit can be the maximum integer value supported by the CPU and Count // Since Limit can be the maximum integer value supported by the CPU and
// can also be the maximum integer value supported by the CPU, this range // Count can also be the maximum integer value supported by the CPU, this
// check must be adjusted to avoid all oveflow conditions. // range check must be adjusted to avoid all oveflow conditions.
// //
// The following form of the range check is equivalent but assumes that // The following form of the range check is equivalent but assumes that
// Limit is of the form (2^n - 1). // Limit is of the form (2^n - 1).
@ -1023,11 +1027,13 @@ RootBridgeIoCheckParameter (
Limit = PrivateData->MemLimit; Limit = PrivateData->MemLimit;
} else { } else {
PciRbAddr = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &Address; PciRbAddr = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &Address;
if (PciRbAddr->Bus < PrivateData->BusBase || PciRbAddr->Bus > PrivateData->BusLimit) { if (PciRbAddr->Bus < PrivateData->BusBase ||
PciRbAddr->Bus > PrivateData->BusLimit) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
if (PciRbAddr->Device > MAX_PCI_DEVICE_NUMBER || PciRbAddr->Function > MAX_PCI_FUNCTION_NUMBER) { if (PciRbAddr->Device > MAX_PCI_DEVICE_NUMBER ||
PciRbAddr->Function > MAX_PCI_FUNCTION_NUMBER) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
@ -1107,7 +1113,8 @@ RootBridgeIoMemRW (
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth; EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth;
UINT8 *Uint8Buffer; UINT8 *Uint8Buffer;
Status = RootBridgeIoCheckParameter (This, MemOperation, Width, Address, Count, Buffer); Status = RootBridgeIoCheckParameter (This, MemOperation, Width, Address,
Count, Buffer);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
return Status; return Status;
} }
@ -1115,7 +1122,9 @@ RootBridgeIoMemRW (
InStride = mInStride[Width]; InStride = mInStride[Width];
OutStride = mOutStride[Width]; OutStride = mOutStride[Width];
OperationWidth = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03); OperationWidth = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);
for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) { for (Uint8Buffer = Buffer;
Count > 0;
Address += InStride, Uint8Buffer += OutStride, Count--) {
if (Write) { if (Write) {
switch (OperationWidth) { switch (OperationWidth) {
case EfiPciWidthUint8: case EfiPciWidthUint8:
@ -1212,7 +1221,8 @@ RootBridgeIoIoRW (
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth; EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth;
UINT8 *Uint8Buffer; UINT8 *Uint8Buffer;
Status = RootBridgeIoCheckParameter (This, IoOperation, Width, Address, Count, Buffer); Status = RootBridgeIoCheckParameter (This, IoOperation, Width, Address,
Count, Buffer);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
return Status; return Status;
} }
@ -1265,7 +1275,9 @@ RootBridgeIoIoRW (
} }
#endif #endif
for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) { for (Uint8Buffer = Buffer;
Count > 0;
Address += InStride, Uint8Buffer += OutStride, Count--) {
if (Write) { if (Write) {
switch (OperationWidth) { switch (OperationWidth) {
case EfiPciWidthUint8: case EfiPciWidthUint8:
@ -1358,7 +1370,8 @@ RootBridgeIoPciRW (
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *PciRbAddr; EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *PciRbAddr;
UINTN PcieRegAddr; UINTN PcieRegAddr;
Status = RootBridgeIoCheckParameter (This, PciOperation, Width, Address, Count, Buffer); Status = RootBridgeIoCheckParameter (This, PciOperation, Width, Address,
Count, Buffer);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
return Status; return Status;
} }
@ -1377,7 +1390,9 @@ RootBridgeIoPciRW (
InStride = mInStride[Width]; InStride = mInStride[Width];
OutStride = mOutStride[Width]; OutStride = mOutStride[Width];
OperationWidth = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03); OperationWidth = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);
for (Uint8Buffer = Buffer; Count > 0; PcieRegAddr += InStride, Uint8Buffer += OutStride, Count--) { for (Uint8Buffer = Buffer;
Count > 0;
PcieRegAddr += InStride, Uint8Buffer += OutStride, Count--) {
if (Write) { if (Write) {
switch (OperationWidth) { switch (OperationWidth) {
case EfiPciWidthUint8: case EfiPciWidthUint8:
@ -1508,14 +1523,16 @@ RootBridgeIoPollMem (
// //
// Determine the proper # of metronome ticks to wait for polling the // Determine the proper # of metronome ticks to wait for polling the
// location. The nuber of ticks is Roundup (Delay / mMetronome->TickPeriod)+1 // location. The nuber of ticks is Roundup (Delay /
// mMetronome->TickPeriod)+1
// The "+1" to account for the possibility of the first tick being short // The "+1" to account for the possibility of the first tick being short
// because we started in the middle of a tick. // because we started in the middle of a tick.
// //
// BugBug: overriding mMetronome->TickPeriod with UINT32 until Metronome // BugBug: overriding mMetronome->TickPeriod with UINT32 until Metronome
// protocol definition is updated. // protocol definition is updated.
// //
NumberOfTicks = DivU64x32Remainder (Delay, (UINT32) mMetronome->TickPeriod, &Remainder); NumberOfTicks = DivU64x32Remainder (Delay, (UINT32) mMetronome->TickPeriod,
&Remainder);
if (Remainder != 0) { if (Remainder != 0) {
NumberOfTicks += 1; NumberOfTicks += 1;
} }
@ -1625,11 +1642,13 @@ RootBridgeIoPollIo (
// //
// Determine the proper # of metronome ticks to wait for polling the // Determine the proper # of metronome ticks to wait for polling the
// location. The number of ticks is Roundup (Delay / mMetronome->TickPeriod)+1 // location. The number of ticks is Roundup (Delay /
// mMetronome->TickPeriod)+1
// The "+1" to account for the possibility of the first tick being short // The "+1" to account for the possibility of the first tick being short
// because we started in the middle of a tick. // because we started in the middle of a tick.
// //
NumberOfTicks = DivU64x32Remainder (Delay, (UINT32)mMetronome->TickPeriod, &Remainder); NumberOfTicks = DivU64x32Remainder (Delay, (UINT32)mMetronome->TickPeriod,
&Remainder);
if (Remainder != 0) { if (Remainder != 0) {
NumberOfTicks += 1; NumberOfTicks += 1;
} }
@ -1895,7 +1914,8 @@ RootBridgeIoCopyMem (
Stride = (UINTN)(1 << Width); Stride = (UINTN)(1 << Width);
Direction = TRUE; Direction = TRUE;
if ((DestAddress > SrcAddress) && (DestAddress < (SrcAddress + Count * Stride))) { if ((DestAddress > SrcAddress) &&
(DestAddress < (SrcAddress + Count * Stride))) {
Direction = FALSE; Direction = FALSE;
SrcAddress = SrcAddress + (Count-1) * Stride; SrcAddress = SrcAddress + (Count-1) * Stride;
DestAddress = DestAddress + (Count-1) * Stride; DestAddress = DestAddress + (Count-1) * Stride;
@ -2093,7 +2113,8 @@ RootBridgeIoMap (
EFI_PHYSICAL_ADDRESS PhysicalAddress; EFI_PHYSICAL_ADDRESS PhysicalAddress;
MAP_INFO *MapInfo; MAP_INFO *MapInfo;
if (HostAddress == NULL || NumberOfBytes == NULL || DeviceAddress == NULL || Mapping == NULL) { if (HostAddress == NULL || NumberOfBytes == NULL || DeviceAddress == NULL ||
Mapping == NULL) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
@ -2122,7 +2143,8 @@ RootBridgeIoMap (
// if above 4GB, then it is not possible to generate a mapping, so return // if above 4GB, then it is not possible to generate a mapping, so return
// an error. // an error.
// //
if (Operation == EfiPciOperationBusMasterCommonBuffer || Operation == EfiPciOperationBusMasterCommonBuffer64) { if (Operation == EfiPciOperationBusMasterCommonBuffer ||
Operation == EfiPciOperationBusMasterCommonBuffer64) {
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
@ -2174,7 +2196,8 @@ RootBridgeIoMap (
// then copy the contents of the real buffer into the mapped buffer // then copy the contents of the real buffer into the mapped buffer
// so the Bus Master can read the contents of the real buffer. // so the Bus Master can read the contents of the real buffer.
// //
if (Operation == EfiPciOperationBusMasterRead || Operation == EfiPciOperationBusMasterRead64) { if (Operation == EfiPciOperationBusMasterRead ||
Operation == EfiPciOperationBusMasterRead64) {
CopyMem ( CopyMem (
(VOID *)(UINTN)MapInfo->MappedHostAddress, (VOID *)(UINTN)MapInfo->MappedHostAddress,
(VOID *)(UINTN)MapInfo->HostAddress, (VOID *)(UINTN)MapInfo->HostAddress,
@ -2188,7 +2211,8 @@ RootBridgeIoMap (
*DeviceAddress = MapInfo->MappedHostAddress; *DeviceAddress = MapInfo->MappedHostAddress;
} else { } else {
// //
// The transfer is below 4GB, so the DeviceAddress is simply the HostAddress // The transfer is below 4GB, so the DeviceAddress is simply the
// HostAddress
// //
*DeviceAddress = PhysicalAddress; *DeviceAddress = PhysicalAddress;
} }
@ -2228,8 +2252,9 @@ RootBridgeIoUnmap (
MAP_INFO *MapInfo; MAP_INFO *MapInfo;
// //
// See if the Map() operation associated with this Unmap() required a mapping buffer. // See if the Map() operation associated with this Unmap() required a mapping
// If a mapping buffer was not required, then this function simply returns EFI_SUCCESS. // buffer. If a mapping buffer was not required, then this function simply
// returns EFI_SUCCESS.
// //
if (Mapping != NULL) { if (Mapping != NULL) {
// //
@ -2242,7 +2267,8 @@ RootBridgeIoUnmap (
// then copy the contents of the mapped buffer into the real buffer // then copy the contents of the mapped buffer into the real buffer
// so the processor can read the contents of the real buffer. // so the processor can read the contents of the real buffer.
// //
if (MapInfo->Operation == EfiPciOperationBusMasterWrite || MapInfo->Operation == EfiPciOperationBusMasterWrite64) { if (MapInfo->Operation == EfiPciOperationBusMasterWrite ||
MapInfo->Operation == EfiPciOperationBusMasterWrite64) {
CopyMem ( CopyMem (
(VOID *)(UINTN)MapInfo->HostAddress, (VOID *)(UINTN)MapInfo->HostAddress,
(VOID *)(UINTN)MapInfo->MappedHostAddress, (VOID *)(UINTN)MapInfo->MappedHostAddress,
@ -2323,9 +2349,11 @@ RootBridgeIoAllocateBuffer (
} }
// //
// The only valid memory types are EfiBootServicesData and EfiRuntimeServicesData // The only valid memory types are EfiBootServicesData and
// EfiRuntimeServicesData
// //
if (MemoryType != EfiBootServicesData && MemoryType != EfiRuntimeServicesData) { if (MemoryType != EfiBootServicesData &&
MemoryType != EfiRuntimeServicesData) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
@ -2334,7 +2362,8 @@ RootBridgeIoAllocateBuffer (
// //
PhysicalAddress = (EFI_PHYSICAL_ADDRESS)(0xffffffff); PhysicalAddress = (EFI_PHYSICAL_ADDRESS)(0xffffffff);
Status = gBS->AllocatePages (AllocateMaxAddress, MemoryType, Pages, &PhysicalAddress); Status = gBS->AllocatePages (AllocateMaxAddress, MemoryType, Pages,
&PhysicalAddress);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
return Status; return Status;
} }
@ -2581,9 +2610,13 @@ RootBridgeIoConfiguration (
for (Index = 0; Index < TypeMax; Index++) { for (Index = 0; Index < TypeMax; Index++) {
if (PrivateData->ResAllocNode[Index].Status == ResAllocated) { if (PrivateData->ResAllocNode[Index].Status == ResAllocated) {
Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->ResAllocNode[Index].Base; EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Desc;
Configuration.SpaceDesp[Index].AddrRangeMax = PrivateData->ResAllocNode[Index].Base + PrivateData->ResAllocNode[Index].Length - 1;
Configuration.SpaceDesp[Index].AddrLen = PrivateData->ResAllocNode[Index].Length; Desc = &Configuration.SpaceDesp[Index];
Desc->AddrRangeMin = PrivateData->ResAllocNode[Index].Base;
Desc->AddrRangeMax = PrivateData->ResAllocNode[Index].Base +
PrivateData->ResAllocNode[Index].Length - 1;
Desc->AddrLen = PrivateData->ResAllocNode[Index].Length;
} }
} }