mirror of https://github.com/acidanthera/audk.git
PcAtChipsetPkg/PciHostBridgeDxe/PciRootBridgeIo.c: rewrap code, strip trailing ws
In this patch the code and the comments embedded in code are rewrapped to 79 columns, plus any trailing whitespace is stripped. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Regression-tested-by: Gabriel Somlo <somlo@cmu.edu> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17950 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Laszlo Ersek
lersek
parent
5c1d397dc2
commit
3cb4bb68e9
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@ -864,10 +864,13 @@ RootBridgeConstructor (
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PrivateData->RootBridgeAttrib = Attri;
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PrivateData->Supports = EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO | EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO | \
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EFI_PCI_ATTRIBUTE_ISA_IO_16 | EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO | \
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EFI_PCI_ATTRIBUTE_VGA_MEMORY | \
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EFI_PCI_ATTRIBUTE_VGA_IO_16 | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;
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PrivateData->Supports = EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO |
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EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO |
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EFI_PCI_ATTRIBUTE_ISA_IO_16 |
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EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO |
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EFI_PCI_ATTRIBUTE_VGA_MEMORY |
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EFI_PCI_ATTRIBUTE_VGA_IO_16 |
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EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;
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PrivateData->Attributes = PrivateData->Supports;
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Protocol->ParentHandle = HostBridgeHandle;
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@ -901,7 +904,8 @@ RootBridgeConstructor (
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Protocol->SegmentNumber = 0;
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Status = gBS->LocateProtocol (&gEfiMetronomeArchProtocolGuid, NULL, (VOID **)&mMetronome);
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Status = gBS->LocateProtocol (&gEfiMetronomeArchProtocolGuid, NULL,
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(VOID **)&mMetronome);
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ASSERT_EFI_ERROR (Status);
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return EFI_SUCCESS;
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@ -1001,16 +1005,16 @@ RootBridgeIoCheckParameter (
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PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);
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//
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// Check to see if any address associated with this transfer exceeds the maximum
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// allowed address. The maximum address implied by the parameters passed in is
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// Address + Size * Count. If the following condition is met, then the transfer
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// is not supported.
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// Check to see if any address associated with this transfer exceeds the
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// maximum allowed address. The maximum address implied by the parameters
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// passed in is Address + Size * Count. If the following condition is met,
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// then the transfer is not supported.
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//
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// Address + Size * Count > Limit + 1
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//
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// Since Limit can be the maximum integer value supported by the CPU and Count
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// can also be the maximum integer value supported by the CPU, this range
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// check must be adjusted to avoid all oveflow conditions.
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// Since Limit can be the maximum integer value supported by the CPU and
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// Count can also be the maximum integer value supported by the CPU, this
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// range check must be adjusted to avoid all oveflow conditions.
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//
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// The following form of the range check is equivalent but assumes that
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// Limit is of the form (2^n - 1).
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@ -1023,11 +1027,13 @@ RootBridgeIoCheckParameter (
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Limit = PrivateData->MemLimit;
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} else {
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PciRbAddr = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &Address;
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if (PciRbAddr->Bus < PrivateData->BusBase || PciRbAddr->Bus > PrivateData->BusLimit) {
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if (PciRbAddr->Bus < PrivateData->BusBase ||
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PciRbAddr->Bus > PrivateData->BusLimit) {
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return EFI_INVALID_PARAMETER;
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}
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if (PciRbAddr->Device > MAX_PCI_DEVICE_NUMBER || PciRbAddr->Function > MAX_PCI_FUNCTION_NUMBER) {
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if (PciRbAddr->Device > MAX_PCI_DEVICE_NUMBER ||
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PciRbAddr->Function > MAX_PCI_FUNCTION_NUMBER) {
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return EFI_INVALID_PARAMETER;
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}
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@ -1107,7 +1113,8 @@ RootBridgeIoMemRW (
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EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth;
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UINT8 *Uint8Buffer;
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Status = RootBridgeIoCheckParameter (This, MemOperation, Width, Address, Count, Buffer);
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Status = RootBridgeIoCheckParameter (This, MemOperation, Width, Address,
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Count, Buffer);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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@ -1115,7 +1122,9 @@ RootBridgeIoMemRW (
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InStride = mInStride[Width];
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OutStride = mOutStride[Width];
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OperationWidth = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);
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for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
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for (Uint8Buffer = Buffer;
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Count > 0;
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Address += InStride, Uint8Buffer += OutStride, Count--) {
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if (Write) {
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switch (OperationWidth) {
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case EfiPciWidthUint8:
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@ -1212,7 +1221,8 @@ RootBridgeIoIoRW (
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EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth;
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UINT8 *Uint8Buffer;
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Status = RootBridgeIoCheckParameter (This, IoOperation, Width, Address, Count, Buffer);
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Status = RootBridgeIoCheckParameter (This, IoOperation, Width, Address,
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Count, Buffer);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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@ -1265,7 +1275,9 @@ RootBridgeIoIoRW (
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}
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#endif
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for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
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for (Uint8Buffer = Buffer;
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Count > 0;
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Address += InStride, Uint8Buffer += OutStride, Count--) {
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if (Write) {
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switch (OperationWidth) {
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case EfiPciWidthUint8:
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@ -1358,7 +1370,8 @@ RootBridgeIoPciRW (
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EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *PciRbAddr;
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UINTN PcieRegAddr;
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Status = RootBridgeIoCheckParameter (This, PciOperation, Width, Address, Count, Buffer);
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Status = RootBridgeIoCheckParameter (This, PciOperation, Width, Address,
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Count, Buffer);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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@ -1377,7 +1390,9 @@ RootBridgeIoPciRW (
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InStride = mInStride[Width];
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OutStride = mOutStride[Width];
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OperationWidth = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);
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for (Uint8Buffer = Buffer; Count > 0; PcieRegAddr += InStride, Uint8Buffer += OutStride, Count--) {
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for (Uint8Buffer = Buffer;
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Count > 0;
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PcieRegAddr += InStride, Uint8Buffer += OutStride, Count--) {
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if (Write) {
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switch (OperationWidth) {
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case EfiPciWidthUint8:
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@ -1508,14 +1523,16 @@ RootBridgeIoPollMem (
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//
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// Determine the proper # of metronome ticks to wait for polling the
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// location. The nuber of ticks is Roundup (Delay / mMetronome->TickPeriod)+1
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// location. The nuber of ticks is Roundup (Delay /
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// mMetronome->TickPeriod)+1
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// The "+1" to account for the possibility of the first tick being short
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// because we started in the middle of a tick.
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//
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// BugBug: overriding mMetronome->TickPeriod with UINT32 until Metronome
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// protocol definition is updated.
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//
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NumberOfTicks = DivU64x32Remainder (Delay, (UINT32) mMetronome->TickPeriod, &Remainder);
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NumberOfTicks = DivU64x32Remainder (Delay, (UINT32) mMetronome->TickPeriod,
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&Remainder);
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if (Remainder != 0) {
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NumberOfTicks += 1;
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}
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@ -1625,11 +1642,13 @@ RootBridgeIoPollIo (
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//
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// Determine the proper # of metronome ticks to wait for polling the
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// location. The number of ticks is Roundup (Delay / mMetronome->TickPeriod)+1
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// location. The number of ticks is Roundup (Delay /
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// mMetronome->TickPeriod)+1
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// The "+1" to account for the possibility of the first tick being short
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// because we started in the middle of a tick.
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//
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NumberOfTicks = DivU64x32Remainder (Delay, (UINT32)mMetronome->TickPeriod, &Remainder);
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NumberOfTicks = DivU64x32Remainder (Delay, (UINT32)mMetronome->TickPeriod,
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&Remainder);
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if (Remainder != 0) {
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NumberOfTicks += 1;
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}
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@ -1895,7 +1914,8 @@ RootBridgeIoCopyMem (
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Stride = (UINTN)(1 << Width);
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Direction = TRUE;
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if ((DestAddress > SrcAddress) && (DestAddress < (SrcAddress + Count * Stride))) {
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if ((DestAddress > SrcAddress) &&
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(DestAddress < (SrcAddress + Count * Stride))) {
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Direction = FALSE;
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SrcAddress = SrcAddress + (Count-1) * Stride;
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DestAddress = DestAddress + (Count-1) * Stride;
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@ -2093,7 +2113,8 @@ RootBridgeIoMap (
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EFI_PHYSICAL_ADDRESS PhysicalAddress;
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MAP_INFO *MapInfo;
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if (HostAddress == NULL || NumberOfBytes == NULL || DeviceAddress == NULL || Mapping == NULL) {
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if (HostAddress == NULL || NumberOfBytes == NULL || DeviceAddress == NULL ||
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Mapping == NULL) {
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return EFI_INVALID_PARAMETER;
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}
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@ -2122,7 +2143,8 @@ RootBridgeIoMap (
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// if above 4GB, then it is not possible to generate a mapping, so return
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// an error.
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//
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if (Operation == EfiPciOperationBusMasterCommonBuffer || Operation == EfiPciOperationBusMasterCommonBuffer64) {
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if (Operation == EfiPciOperationBusMasterCommonBuffer ||
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Operation == EfiPciOperationBusMasterCommonBuffer64) {
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return EFI_UNSUPPORTED;
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}
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@ -2174,7 +2196,8 @@ RootBridgeIoMap (
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// then copy the contents of the real buffer into the mapped buffer
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// so the Bus Master can read the contents of the real buffer.
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//
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if (Operation == EfiPciOperationBusMasterRead || Operation == EfiPciOperationBusMasterRead64) {
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if (Operation == EfiPciOperationBusMasterRead ||
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Operation == EfiPciOperationBusMasterRead64) {
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CopyMem (
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(VOID *)(UINTN)MapInfo->MappedHostAddress,
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(VOID *)(UINTN)MapInfo->HostAddress,
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@ -2188,7 +2211,8 @@ RootBridgeIoMap (
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*DeviceAddress = MapInfo->MappedHostAddress;
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} else {
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//
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// The transfer is below 4GB, so the DeviceAddress is simply the HostAddress
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// The transfer is below 4GB, so the DeviceAddress is simply the
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// HostAddress
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//
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*DeviceAddress = PhysicalAddress;
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}
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@ -2228,8 +2252,9 @@ RootBridgeIoUnmap (
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MAP_INFO *MapInfo;
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//
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// See if the Map() operation associated with this Unmap() required a mapping buffer.
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// If a mapping buffer was not required, then this function simply returns EFI_SUCCESS.
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// See if the Map() operation associated with this Unmap() required a mapping
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// buffer. If a mapping buffer was not required, then this function simply
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// returns EFI_SUCCESS.
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//
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if (Mapping != NULL) {
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//
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@ -2242,7 +2267,8 @@ RootBridgeIoUnmap (
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// then copy the contents of the mapped buffer into the real buffer
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// so the processor can read the contents of the real buffer.
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//
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if (MapInfo->Operation == EfiPciOperationBusMasterWrite || MapInfo->Operation == EfiPciOperationBusMasterWrite64) {
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if (MapInfo->Operation == EfiPciOperationBusMasterWrite ||
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MapInfo->Operation == EfiPciOperationBusMasterWrite64) {
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CopyMem (
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(VOID *)(UINTN)MapInfo->HostAddress,
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(VOID *)(UINTN)MapInfo->MappedHostAddress,
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@ -2323,9 +2349,11 @@ RootBridgeIoAllocateBuffer (
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}
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//
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// The only valid memory types are EfiBootServicesData and EfiRuntimeServicesData
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// The only valid memory types are EfiBootServicesData and
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// EfiRuntimeServicesData
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//
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if (MemoryType != EfiBootServicesData && MemoryType != EfiRuntimeServicesData) {
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if (MemoryType != EfiBootServicesData &&
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MemoryType != EfiRuntimeServicesData) {
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return EFI_INVALID_PARAMETER;
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}
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@ -2334,7 +2362,8 @@ RootBridgeIoAllocateBuffer (
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//
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PhysicalAddress = (EFI_PHYSICAL_ADDRESS)(0xffffffff);
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Status = gBS->AllocatePages (AllocateMaxAddress, MemoryType, Pages, &PhysicalAddress);
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Status = gBS->AllocatePages (AllocateMaxAddress, MemoryType, Pages,
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&PhysicalAddress);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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@ -2581,9 +2610,13 @@ RootBridgeIoConfiguration (
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for (Index = 0; Index < TypeMax; Index++) {
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if (PrivateData->ResAllocNode[Index].Status == ResAllocated) {
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Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->ResAllocNode[Index].Base;
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Configuration.SpaceDesp[Index].AddrRangeMax = PrivateData->ResAllocNode[Index].Base + PrivateData->ResAllocNode[Index].Length - 1;
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Configuration.SpaceDesp[Index].AddrLen = PrivateData->ResAllocNode[Index].Length;
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EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Desc;
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Desc = &Configuration.SpaceDesp[Index];
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Desc->AddrRangeMin = PrivateData->ResAllocNode[Index].Base;
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Desc->AddrRangeMax = PrivateData->ResAllocNode[Index].Base +
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PrivateData->ResAllocNode[Index].Length - 1;
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Desc->AddrLen = PrivateData->ResAllocNode[Index].Length;
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}
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}
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