mirror of https://github.com/acidanthera/audk.git
MdeModulePkg PiDxeS3BootScriptLib: Support multiple PCI segment
Support multiple PCI segment for PCI_CONFIG2 opcodes. PiDxeS3BootScriptLib needs to be updated to consume PciSegmentLib instead of PciLib. That means platforms need to add PciSegmentLib declaration like below in platform dsc if the PciSegmentLib was not declared in platform dsc before. PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf For platforms only have one segment, MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf is recommended to be used and declared in platform dsc for PiDxeS3BootScriptLib to have equivalent functionality with before. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Amy Chan <amy.chan@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com>
This commit is contained in:
Star Zeng
parent
3a03e95eda
commit
3d20524af0
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@ -1,7 +1,7 @@
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/** @file
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Interpret and execute the S3 data in S3 boot script.
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Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions
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@ -639,9 +639,10 @@ BootScriptExecuteMemoryWrite (
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}
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/**
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Performance PCI configuration read operation
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Performance PCI configuration 2 read operation
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@param Width Width of the operation.
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@param Segment Pci segment number
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@param Address Address of the operation.
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@param Count Count of the number of accesses to perform.
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@param Buffer Pointer to the buffer read from PCI config space
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@ -652,8 +653,9 @@ BootScriptExecuteMemoryWrite (
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**/
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EFI_STATUS
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ScriptPciCfgRead (
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ScriptPciCfg2Read (
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IN S3_BOOT_SCRIPT_LIB_WIDTH Width,
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IN UINT16 Segment,
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IN UINT64 Address,
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IN UINTN Count,
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OUT VOID *Buffer
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@ -663,11 +665,11 @@ ScriptPciCfgRead (
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UINTN AddressStride;
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UINTN BufferStride;
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PTR Out;
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UINTN PciAddress;
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UINT64 PciAddress;
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Out.Buf = (UINT8 *) Buffer;
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PciAddress = PCI_ADDRESS_ENCODE (Address);
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PciAddress = PCI_ADDRESS_ENCODE (Segment, Address);
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Status = BuildLoopData (Width, PciAddress, &AddressStride, &BufferStride);
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if (EFI_ERROR (Status)) {
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@ -679,42 +681,42 @@ ScriptPciCfgRead (
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for (; Count > 0; Count--, PciAddress += AddressStride, Out.Buf += BufferStride) {
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switch (Width) {
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case S3BootScriptWidthUint8:
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DEBUG ((EFI_D_INFO, "S3BootScriptWidthUint8 - 0x%08x\n", PciAddress));
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*Out.Uint8 = PciRead8 (PciAddress);
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DEBUG ((EFI_D_INFO, "S3BootScriptWidthUint8 - 0x%016lx\n", PciAddress));
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*Out.Uint8 = PciSegmentRead8 (PciAddress);
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break;
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case S3BootScriptWidthFifoUint8:
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DEBUG ((EFI_D_INFO, "S3BootScriptWidthFifoUint8 - 0x%08x\n", PciAddress));
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*Out.Uint8 = PciRead8 (PciAddress);
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DEBUG ((EFI_D_INFO, "S3BootScriptWidthFifoUint8 - 0x%016lx\n", PciAddress));
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*Out.Uint8 = PciSegmentRead8 (PciAddress);
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break;
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case S3BootScriptWidthFillUint8:
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DEBUG ((EFI_D_INFO, "S3BootScriptWidthFillUint8 - 0x%08x\n", PciAddress));
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*Out.Uint8 = PciRead8 (PciAddress);
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DEBUG ((EFI_D_INFO, "S3BootScriptWidthFillUint8 - 0x%016lx\n", PciAddress));
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*Out.Uint8 = PciSegmentRead8 (PciAddress);
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break;
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case S3BootScriptWidthUint16:
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DEBUG ((EFI_D_INFO, "S3BootScriptWidthUint16 - 0x%08x\n", PciAddress));
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*Out.Uint16 = PciRead16 (PciAddress);
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DEBUG ((EFI_D_INFO, "S3BootScriptWidthUint16 - 0x%016lx\n", PciAddress));
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*Out.Uint16 = PciSegmentRead16 (PciAddress);
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break;
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case S3BootScriptWidthFifoUint16:
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DEBUG ((EFI_D_INFO, "S3BootScriptWidthFifoUint16 - 0x%08x\n", PciAddress));
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*Out.Uint16 = PciRead16 (PciAddress);
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DEBUG ((EFI_D_INFO, "S3BootScriptWidthFifoUint16 - 0x%016lx\n", PciAddress));
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*Out.Uint16 = PciSegmentRead16 (PciAddress);
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break;
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case S3BootScriptWidthFillUint16:
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DEBUG ((EFI_D_INFO, "S3BootScriptWidthFillUint16 - 0x%08x\n", PciAddress));
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*Out.Uint16 = PciRead16 (PciAddress);
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DEBUG ((EFI_D_INFO, "S3BootScriptWidthFillUint16 - 0x%016lx\n", PciAddress));
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*Out.Uint16 = PciSegmentRead16 (PciAddress);
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break;
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case S3BootScriptWidthUint32:
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DEBUG ((EFI_D_INFO, "S3BootScriptWidthUint32 - 0x%08x\n", PciAddress));
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*Out.Uint32 = PciRead32 (PciAddress);
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DEBUG ((EFI_D_INFO, "S3BootScriptWidthUint32 - 0x%016lx\n", PciAddress));
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*Out.Uint32 = PciSegmentRead32 (PciAddress);
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break;
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case S3BootScriptWidthFifoUint32:
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DEBUG ((EFI_D_INFO, "S3BootScriptWidthFifoUint32 - 0x%08x\n", PciAddress));
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*Out.Uint32 = PciRead32 (PciAddress);
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DEBUG ((EFI_D_INFO, "S3BootScriptWidthFifoUint32 - 0x%016lx\n", PciAddress));
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*Out.Uint32 = PciSegmentRead32 (PciAddress);
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break;
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case S3BootScriptWidthFillUint32:
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DEBUG ((EFI_D_INFO, "S3BootScriptWidthFillUint32 - 0x%08x\n", PciAddress));
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*Out.Uint32 = PciRead32 (PciAddress);
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DEBUG ((EFI_D_INFO, "S3BootScriptWidthFillUint32 - 0x%016lx\n", PciAddress));
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*Out.Uint32 = PciSegmentRead32 (PciAddress);
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break;
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default:
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@ -725,9 +727,10 @@ ScriptPciCfgRead (
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}
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/**
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Performance PCI configuration write operation
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Performance PCI configuration 2 write operation
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@param Width Width of the operation.
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@param Segment Pci segment number
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@param Address Address of the operation.
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@param Count Count of the number of accesses to perform.
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@param Buffer Pointer to the buffer write to PCI config space
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@ -738,8 +741,9 @@ ScriptPciCfgRead (
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**/
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EFI_STATUS
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ScriptPciCfgWrite (
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ScriptPciCfg2Write (
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IN S3_BOOT_SCRIPT_LIB_WIDTH Width,
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IN UINT16 Segment,
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IN UINT64 Address,
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IN UINTN Count,
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IN VOID *Buffer
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@ -748,14 +752,14 @@ ScriptPciCfgWrite (
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EFI_STATUS Status;
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UINTN AddressStride;
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UINTN BufferStride;
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UINTN OriginalPciAddress;
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UINT64 OriginalPciAddress;
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PTR In;
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PTR OriginalIn;
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UINTN PciAddress;
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UINT64 PciAddress;
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In.Buf = (UINT8 *) Buffer;
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PciAddress = PCI_ADDRESS_ENCODE (Address);
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PciAddress = PCI_ADDRESS_ENCODE (Segment, Address);
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Status = BuildLoopData (Width, PciAddress, &AddressStride, &BufferStride);
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if (EFI_ERROR (Status)) {
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@ -769,40 +773,40 @@ ScriptPciCfgWrite (
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for (; Count > 0; Count--, PciAddress += AddressStride, In.Buf += BufferStride) {
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switch (Width) {
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case S3BootScriptWidthUint8:
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DEBUG ((EFI_D_INFO, "S3BootScriptWidthUint8 - 0x%08x (0x%02x)\n", PciAddress, (UINTN)*In.Uint8));
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PciWrite8 (PciAddress, *In.Uint8);
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DEBUG ((EFI_D_INFO, "S3BootScriptWidthUint8 - 0x%016lx (0x%02x)\n", PciAddress, (UINTN)*In.Uint8));
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PciSegmentWrite8 (PciAddress, *In.Uint8);
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break;
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case S3BootScriptWidthFifoUint8:
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DEBUG ((EFI_D_INFO, "S3BootScriptWidthFifoUint8 - 0x%08x (0x%02x)\n", OriginalPciAddress, (UINTN)*In.Uint8));
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PciWrite8 (OriginalPciAddress, *In.Uint8);
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DEBUG ((EFI_D_INFO, "S3BootScriptWidthFifoUint8 - 0x%016lx (0x%02x)\n", OriginalPciAddress, (UINTN)*In.Uint8));
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PciSegmentWrite8 (OriginalPciAddress, *In.Uint8);
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break;
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case S3BootScriptWidthFillUint8:
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DEBUG ((EFI_D_INFO, "S3BootScriptWidthFillUint8 - 0x%08x (0x%02x)\n", PciAddress, (UINTN)*OriginalIn.Uint8));
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PciWrite8 (PciAddress, *OriginalIn.Uint8);
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DEBUG ((EFI_D_INFO, "S3BootScriptWidthFillUint8 - 0x%016lx (0x%02x)\n", PciAddress, (UINTN)*OriginalIn.Uint8));
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PciSegmentWrite8 (PciAddress, *OriginalIn.Uint8);
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break;
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case S3BootScriptWidthUint16:
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DEBUG ((EFI_D_INFO, "S3BootScriptWidthUint16 - 0x%08x (0x%04x)\n", PciAddress, (UINTN)*In.Uint16));
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PciWrite16 (PciAddress, *In.Uint16);
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DEBUG ((EFI_D_INFO, "S3BootScriptWidthUint16 - 0x%016lx (0x%04x)\n", PciAddress, (UINTN)*In.Uint16));
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PciSegmentWrite16 (PciAddress, *In.Uint16);
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break;
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case S3BootScriptWidthFifoUint16:
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DEBUG ((EFI_D_INFO, "S3BootScriptWidthFifoUint16 - 0x%08x (0x%04x)\n", OriginalPciAddress, (UINTN)*In.Uint16));
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PciWrite16 (OriginalPciAddress, *In.Uint16);
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DEBUG ((EFI_D_INFO, "S3BootScriptWidthFifoUint16 - 0x%016lx (0x%04x)\n", OriginalPciAddress, (UINTN)*In.Uint16));
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PciSegmentWrite16 (OriginalPciAddress, *In.Uint16);
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break;
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case S3BootScriptWidthFillUint16:
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DEBUG ((EFI_D_INFO, "S3BootScriptWidthFillUint16 - 0x%08x (0x%04x)\n", PciAddress, (UINTN)*OriginalIn.Uint16));
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PciWrite16 (PciAddress, *OriginalIn.Uint16);
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DEBUG ((EFI_D_INFO, "S3BootScriptWidthFillUint16 - 0x%016lx (0x%04x)\n", PciAddress, (UINTN)*OriginalIn.Uint16));
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PciSegmentWrite16 (PciAddress, *OriginalIn.Uint16);
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break;
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case S3BootScriptWidthUint32:
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DEBUG ((EFI_D_INFO, "S3BootScriptWidthUint32 - 0x%08x (0x%08x)\n", PciAddress, (UINTN)*In.Uint32));
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PciWrite32 (PciAddress, *In.Uint32);
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DEBUG ((EFI_D_INFO, "S3BootScriptWidthUint32 - 0x%016lx (0x%08x)\n", PciAddress, (UINTN)*In.Uint32));
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PciSegmentWrite32 (PciAddress, *In.Uint32);
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break;
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case S3BootScriptWidthFifoUint32:
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DEBUG ((EFI_D_INFO, "S3BootScriptWidthFifoUint32 - 0x%08x (0x%08x)\n", OriginalPciAddress, (UINTN)*In.Uint32));
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PciWrite32 (OriginalPciAddress, *In.Uint32);
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DEBUG ((EFI_D_INFO, "S3BootScriptWidthFifoUint32 - 0x%016lx (0x%08x)\n", OriginalPciAddress, (UINTN)*In.Uint32));
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PciSegmentWrite32 (OriginalPciAddress, *In.Uint32);
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break;
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case S3BootScriptWidthFillUint32:
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DEBUG ((EFI_D_INFO, "S3BootScriptWidthFillUint32 - 0x%08x (0x%08x)\n", (UINTN)PciAddress, (UINTN)*OriginalIn.Uint32));
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PciWrite32 (PciAddress, *OriginalIn.Uint32);
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DEBUG ((EFI_D_INFO, "S3BootScriptWidthFillUint32 - 0x%016lx (0x%08x)\n", (UINTN)PciAddress, (UINTN)*OriginalIn.Uint32));
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PciSegmentWrite32 (PciAddress, *OriginalIn.Uint32);
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break;
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default:
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return EFI_INVALID_PARAMETER;
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@ -811,10 +815,9 @@ ScriptPciCfgWrite (
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return EFI_SUCCESS;
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}
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/**
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Performance PCI configuration 2 read operation
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Performance PCI configuration read operation
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@param Width Width of the operation.
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@param Segment Pci segment number
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@param Address Address of the operation.
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@param Count Count of the number of accesses to perform.
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@param Buffer Pointer to the buffer to read from PCI config space.
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@ -824,27 +827,22 @@ ScriptPciCfgWrite (
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Buffer is NULL.
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The Buffer is not aligned for the given Width.
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Address is outside the legal range of I/O ports.
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@note A known Limitations in the implementation which is the 'Segment' parameter is assumed as
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Zero, or else, assert.
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**/
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EFI_STATUS
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ScriptPciCfg2Read (
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ScriptPciCfgRead (
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IN S3_BOOT_SCRIPT_LIB_WIDTH Width,
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IN UINT16 Segment,
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IN UINT64 Address,
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IN UINTN Count,
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OUT VOID *Buffer
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)
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{
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ASSERT (Segment==0);
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return ScriptPciCfgRead (Width, Address, Count, Buffer);
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return ScriptPciCfg2Read (Width, 0, Address, Count, Buffer);
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}
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/**
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Performance PCI configuration 2 write operation
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Performance PCI configuration write operation
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@param Width Width of the operation.
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@param Segment Pci segment number
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@param Address Address of the operation.
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@param Count Count of the number of accesses to perform.
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@param Buffer Pointer to the buffer to write to PCI config space.
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@ -854,22 +852,18 @@ ScriptPciCfg2Read (
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Buffer is NULL.
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The Buffer is not aligned for the given Width.
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Address is outside the legal range of I/O ports.
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@note A known Limitations in the implementation which is the 'Segment' parameter is assumed as
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Zero, or else, assert.
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**/
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EFI_STATUS
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EFIAPI
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ScriptPciCfg2Write (
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ScriptPciCfgWrite (
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IN S3_BOOT_SCRIPT_LIB_WIDTH Width,
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IN UINT16 Segment,
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IN UINT64 Address,
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IN UINTN Count,
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IN VOID *Buffer
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)
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{
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ASSERT (Segment==0);
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return ScriptPciCfgWrite (Width, Address, Count, Buffer);
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return ScriptPciCfg2Write (Width, 0, Address, Count, Buffer);
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}
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/**
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Interprete the boot script node with EFI_BOOT_SCRIPT_PCI_CONFIG_WRITE OP code.
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@ -896,7 +890,7 @@ BootScriptExecutePciCfgWrite (
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Count = PciCfgWrite.Count;
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Buffer = Script + sizeof(EFI_BOOT_SCRIPT_PCI_CONFIG_WRITE);
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DEBUG ((EFI_D_INFO, "BootScriptExecutePciCfgWrite - 0x%08x, 0x%08x, 0x%08x\n", PCI_ADDRESS_ENCODE (Address), Count, (UINTN)Width));
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DEBUG ((EFI_D_INFO, "BootScriptExecutePciCfgWrite - 0x%016lx, 0x%08x, 0x%08x\n", PCI_ADDRESS_ENCODE (0, Address), Count, (UINTN)Width));
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return ScriptPciCfgWrite (Width, Address, Count, Buffer);
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}
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/**
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@ -1012,7 +1006,7 @@ BootScriptExecutePciCfgReadWrite (
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CopyMem((VOID*)&PciCfgReadWrite, (VOID*)Script, sizeof(EFI_BOOT_SCRIPT_PCI_CONFIG_READ_WRITE));
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DEBUG ((EFI_D_INFO, "BootScriptExecutePciCfgReadWrite - 0x%08x, 0x%016lx, 0x%016lx\n", PCI_ADDRESS_ENCODE (PciCfgReadWrite.Address), AndMask, OrMask));
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DEBUG ((EFI_D_INFO, "BootScriptExecutePciCfgReadWrite - 0x%016lx, 0x%016lx, 0x%016lx\n", PCI_ADDRESS_ENCODE (0, PciCfgReadWrite.Address), AndMask, OrMask));
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Status = ScriptPciCfgRead (
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(S3_BOOT_SCRIPT_LIB_WIDTH) PciCfgReadWrite.Width,
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@ -1422,7 +1416,7 @@ BootScriptExecutePciCfg2Write (
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Count = PciCfg2Write.Count;
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Buffer = Script + sizeof(EFI_BOOT_SCRIPT_PCI_CONFIG2_WRITE);
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DEBUG ((EFI_D_INFO, "BootScriptExecutePciCfg2Write - 0x%04x, 0x%08x, 0x%08x, 0x%08x\n", Segment, PCI_ADDRESS_ENCODE (Address), Count, (UINTN)Width));
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DEBUG ((EFI_D_INFO, "BootScriptExecutePciCfg2Write - 0x%016lx, 0x%08x, 0x%08x\n", PCI_ADDRESS_ENCODE (Segment, Address), Count, (UINTN)Width));
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return ScriptPciCfg2Write (Width, Segment, Address, Count, Buffer);
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}
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@ -1452,7 +1446,7 @@ BootScriptExecutePciCfg2ReadWrite (
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CopyMem ((VOID*)&PciCfg2ReadWrite, (VOID*)Script, sizeof(EFI_BOOT_SCRIPT_PCI_CONFIG2_READ_WRITE));
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DEBUG ((EFI_D_INFO, "BootScriptExecutePciCfg2ReadWrite - 0x%04x, 0x%08x, 0x%016lx, 0x%016lx\n", PciCfg2ReadWrite.Segment, PCI_ADDRESS_ENCODE (PciCfg2ReadWrite.Address), AndMask, OrMask));
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DEBUG ((EFI_D_INFO, "BootScriptExecutePciCfg2ReadWrite - 0x%016lx, 0x%016lx, 0x%016lx\n", PCI_ADDRESS_ENCODE (PciCfg2ReadWrite.Segment, PciCfg2ReadWrite.Address), AndMask, OrMask));
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Status = ScriptPciCfg2Read (
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(S3_BOOT_SCRIPT_LIB_WIDTH) PciCfg2ReadWrite.Width,
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@ -1499,7 +1493,7 @@ BootScriptPciCfgPoll (
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EFI_BOOT_SCRIPT_PCI_CONFIG_POLL PciCfgPoll;
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CopyMem ((VOID*)&PciCfgPoll, (VOID*)Script, sizeof(EFI_BOOT_SCRIPT_PCI_CONFIG_POLL));
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DEBUG ((EFI_D_INFO, "BootScriptPciCfgPoll - 0x%08x, 0x%016lx, 0x%016lx\n", PCI_ADDRESS_ENCODE (PciCfgPoll.Address), AndMask, OrMask));
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DEBUG ((EFI_D_INFO, "BootScriptPciCfgPoll - 0x%016lx, 0x%016lx, 0x%016lx\n", PCI_ADDRESS_ENCODE (0, PciCfgPoll.Address), AndMask, OrMask));
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Data = 0;
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Status = ScriptPciCfgRead (
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@ -1561,7 +1555,7 @@ BootScriptPciCfg2Poll (
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Data = 0;
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CopyMem ((VOID*)&PciCfg2Poll, (VOID*)Script, sizeof(EFI_BOOT_SCRIPT_PCI_CONFIG2_POLL));
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DEBUG ((EFI_D_INFO, "BootScriptPciCfg2Poll - 0x%04x, 0x%08x, 0x%016lx, 0x%016lx\n", PciCfg2Poll.Segment, PCI_ADDRESS_ENCODE (PciCfg2Poll.Address), AndMask, OrMask));
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DEBUG ((EFI_D_INFO, "BootScriptPciCfg2Poll - 0x%016lx, 0x%016lx, 0x%016lx\n", PCI_ADDRESS_ENCODE (PciCfg2Poll.Segment, PciCfg2Poll.Address), AndMask, OrMask));
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Status = ScriptPciCfg2Read (
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(S3_BOOT_SCRIPT_LIB_WIDTH) PciCfg2Poll.Width,
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@ -1604,9 +1598,6 @@ BootScriptPciCfg2Poll (
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@retval RETURN_SUCCESS The boot script table was executed successfully.
|
||||
@retval RETURN_UNSUPPORTED Invalid script table or opcode.
|
||||
|
||||
@note A known Limitations in the implementation: When interpreting the opcode EFI_BOOT_SCRIPT_PCI_CONFIG2_WRITE_OPCODE
|
||||
EFI_BOOT_SCRIPT_PCI_CONFIG2_READ_WRITE_OPCODE and EFI_BOOT_SCRIPT_PCI_CONFIG2_POLL_OPCODE, the 'Segment' parameter is assumed as
|
||||
Zero, or else, assert.
|
||||
**/
|
||||
RETURN_STATUS
|
||||
EFIAPI
|
||||
|
|
|
|||
|
|
@ -1291,7 +1291,7 @@ S3BootScriptSavePciCfgReadWrite (
|
|||
|
||||
@retval RETURN_OUT_OF_RESOURCES Not enough memory for the table do operation.
|
||||
@retval RETURN_SUCCESS Opcode is added.
|
||||
@note A known Limitations in the implementation which is non-zero Segment and 64bits operations are not supported.
|
||||
@note A known Limitations in the implementation which is 64bits operations are not supported.
|
||||
|
||||
**/
|
||||
RETURN_STATUS
|
||||
|
|
@ -1309,8 +1309,7 @@ S3BootScriptSavePciCfg2Write (
|
|||
UINT8 WidthInByte;
|
||||
EFI_BOOT_SCRIPT_PCI_CONFIG2_WRITE ScriptPciWrite2;
|
||||
|
||||
if (Segment != 0 ||
|
||||
Width == S3BootScriptWidthUint64 ||
|
||||
if (Width == S3BootScriptWidthUint64 ||
|
||||
Width == S3BootScriptWidthFifoUint64 ||
|
||||
Width == S3BootScriptWidthFillUint64) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
|
|
@ -1351,7 +1350,7 @@ S3BootScriptSavePciCfg2Write (
|
|||
|
||||
@retval RETURN_OUT_OF_RESOURCES Not enough memory for the table do operation.
|
||||
@retval RETURN_SUCCESS Opcode is added.
|
||||
@note A known Limitations in the implementation which is non-zero Segment and 64bits operations are not supported.
|
||||
@note A known Limitations in the implementation which is 64bits operations are not supported.
|
||||
|
||||
**/
|
||||
RETURN_STATUS
|
||||
|
|
@ -1369,8 +1368,7 @@ S3BootScriptSavePciCfg2ReadWrite (
|
|||
UINT8 WidthInByte;
|
||||
EFI_BOOT_SCRIPT_PCI_CONFIG2_READ_WRITE ScriptPciReadWrite2;
|
||||
|
||||
if (Segment != 0 ||
|
||||
Width == S3BootScriptWidthUint64 ||
|
||||
if (Width == S3BootScriptWidthUint64 ||
|
||||
Width == S3BootScriptWidthFifoUint64 ||
|
||||
Width == S3BootScriptWidthFillUint64) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
|
|
@ -1946,7 +1944,7 @@ S3BootScriptSavePciPoll (
|
|||
|
||||
@retval RETURN_OUT_OF_RESOURCES Not enough memory for the table do operation.
|
||||
@retval RETURN_SUCCESS Opcode is added.
|
||||
@note A known Limitations in the implementation which is non-zero Segment and 64bits operations are not supported.
|
||||
@note A known Limitations in the implementation which is 64bits operations are not supported.
|
||||
|
||||
**/
|
||||
RETURN_STATUS
|
||||
|
|
@ -1965,8 +1963,7 @@ S3BootScriptSavePci2Poll (
|
|||
UINT8 Length;
|
||||
EFI_BOOT_SCRIPT_PCI_CONFIG2_POLL ScriptPci2Poll;
|
||||
|
||||
if (Segment != 0 ||
|
||||
Width == S3BootScriptWidthUint64 ||
|
||||
if (Width == S3BootScriptWidthUint64 ||
|
||||
Width == S3BootScriptWidthFifoUint64 ||
|
||||
Width == S3BootScriptWidthFillUint64) {
|
||||
return EFI_INVALID_PARAMETER;
|
||||
|
|
|
|||
|
|
@ -52,7 +52,7 @@
|
|||
PcdLib
|
||||
UefiLib
|
||||
SmbusLib
|
||||
PciLib
|
||||
PciSegmentLib
|
||||
IoLib
|
||||
LockBoxLib
|
||||
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
Support for S3 boot script lib. This file defined some internal macro and internal
|
||||
data structure
|
||||
|
||||
Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
|
||||
Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
|
||||
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions
|
||||
|
|
@ -33,7 +33,7 @@
|
|||
#include <Library/PcdLib.h>
|
||||
#include <Library/SmbusLib.h>
|
||||
#include <Library/IoLib.h>
|
||||
#include <Library/PciLib.h>
|
||||
#include <Library/PciSegmentLib.h>
|
||||
#include <Library/DebugLib.h>
|
||||
#include <Library/BaseMemoryLib.h>
|
||||
#include <Library/TimerLib.h>
|
||||
|
|
@ -45,14 +45,16 @@
|
|||
#define MAX_IO_ADDRESS 0xFFFF
|
||||
|
||||
//
|
||||
// Macro to convert a UEFI PCI address to a PCI Library PCI address
|
||||
// Macro to convert a UEFI PCI address + segment to a PCI Segment Library PCI address
|
||||
//
|
||||
#define PCI_ADDRESS_ENCODE(A) (UINTN)PCI_LIB_ADDRESS( \
|
||||
((((UINTN)(A))& 0xff000000) >> 24), ((((UINTN)(A)) &0x00ff0000) >> 16), ((((UINTN)(A)) & 0xff00) >> 8), ((RShiftU64 ((A), 32) & 0xfff) | ((A)& 0xff)) \
|
||||
#define PCI_ADDRESS_ENCODE(S, A) PCI_SEGMENT_LIB_ADDRESS( \
|
||||
S, \
|
||||
((((UINTN)(A)) & 0xff000000) >> 24), \
|
||||
((((UINTN)(A)) & 0x00ff0000) >> 16), \
|
||||
((((UINTN)(A)) & 0xff00) >> 8), \
|
||||
((RShiftU64 ((A), 32) & 0xfff) | ((A) & 0xff)) \
|
||||
)
|
||||
|
||||
|
||||
|
||||
typedef union {
|
||||
UINT8 volatile *Buf;
|
||||
UINT8 volatile *Uint8;
|
||||
|
|
|
|||
Loading…
Reference in New Issue