tyler.durden
/
audk
mirror of https://github.com/acidanthera/audk.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridge.c: rewrap code, strip trailing ws 

In this patch the code and the comments embedded in code are rewrapped to
79 columns, plus any trailing whitespace is stripped.

Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Regression-tested-by: Gabriel Somlo <somlo@cmu.edu>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17948 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Laszlo Ersek 2015-07-14 12:01:21 +00:00 committed by lersek
parent 7c7af556e0
commit 3d9eddb1b7
1 changed files with 218 additions and 179 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

103
PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridge.c
View File

@ -24,7 +24,9 @@
// //
UINTN RootBridgeNumber[1] = { 1 }; UINTN RootBridgeNumber[1] = { 1 };
UINT64 RootBridgeAttribute[1][1] = { { EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM } }; UINT64 RootBridgeAttribute[1][1] = {
{ EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM }
};
EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[1][1] = { EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[1][1] = {
{ {
@ -112,7 +114,8 @@ InitializePciHostBridge (
// Create Host Bridge Device Handle // Create Host Bridge Device Handle
// //
for (Loop1 = 0; Loop1 < HOST_BRIDGE_NUMBER; Loop1++) { for (Loop1 = 0; Loop1 < HOST_BRIDGE_NUMBER; Loop1++) {
HostBridge = AllocateCopyPool (sizeof(PCI_HOST_BRIDGE_INSTANCE), &mPciHostBridgeInstanceTemplate); HostBridge = AllocateCopyPool (sizeof(PCI_HOST_BRIDGE_INSTANCE),
&mPciHostBridgeInstanceTemplate);
if (HostBridge == NULL) { if (HostBridge == NULL) {
return EFI_OUT_OF_RESOURCES; return EFI_OUT_OF_RESOURCES;
} }
@ -122,7 +125,8 @@ InitializePciHostBridge (
Status = gBS->InstallMultipleProtocolInterfaces ( Status = gBS->InstallMultipleProtocolInterfaces (
&HostBridge->HostBridgeHandle, &HostBridge->HostBridgeHandle,
&gEfiPciHostBridgeResourceAllocationProtocolGuid, &HostBridge->ResAlloc, &gEfiPciHostBridgeResourceAllocationProtocolGuid,
&HostBridge->ResAlloc,
NULL NULL
); );
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
@ -141,7 +145,8 @@ InitializePciHostBridge (
} }
PrivateData->Signature = PCI_ROOT_BRIDGE_SIGNATURE; PrivateData->Signature = PCI_ROOT_BRIDGE_SIGNATURE;
PrivateData->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[Loop1][Loop2]; PrivateData->DevicePath =
(EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[Loop1][Loop2];
RootBridgeConstructor ( RootBridgeConstructor (
&PrivateData->Io, &PrivateData->Io,
@ -152,8 +157,10 @@ InitializePciHostBridge (
Status = gBS->InstallMultipleProtocolInterfaces( Status = gBS->InstallMultipleProtocolInterfaces(
&PrivateData->Handle, &PrivateData->Handle,
&gEfiDevicePathProtocolGuid, PrivateData->DevicePath, &gEfiDevicePathProtocolGuid,
&gEfiPciRootBridgeIoProtocolGuid, &PrivateData->Io, PrivateData->DevicePath,
&gEfiPciRootBridgeIoProtocolGuid,
&PrivateData->Io,
NULL NULL
); );
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
@ -334,21 +341,24 @@ NotifyPhase(
case EfiPciHostBridgeBeginBusAllocation: case EfiPciHostBridgeBeginBusAllocation:
// //
// No specific action is required here, can perform any chipset specific programing // No specific action is required here, can perform any chipset specific
// programing
// //
HostBridgeInstance->CanRestarted = FALSE; HostBridgeInstance->CanRestarted = FALSE;
break; break;
case EfiPciHostBridgeEndBusAllocation: case EfiPciHostBridgeEndBusAllocation:
// //
// No specific action is required here, can perform any chipset specific programing // No specific action is required here, can perform any chipset specific
// programing
// //
//HostBridgeInstance->CanRestarted = FALSE; //HostBridgeInstance->CanRestarted = FALSE;
break; break;
case EfiPciHostBridgeBeginResourceAllocation: case EfiPciHostBridgeBeginResourceAllocation:
// //
// No specific action is required here, can perform any chipset specific programing // No specific action is required here, can perform any chipset specific
// programing
// //
//HostBridgeInstance->CanRestarted = FALSE; //HostBridgeInstance->CanRestarted = FALSE;
break; break;
@ -371,7 +381,10 @@ NotifyPhase(
// //
// Get the number of '1' in Alignment. // Get the number of '1' in Alignment.
// //
BitsOfAlignment = (UINTN) (HighBitSet64 (RootBridgeInstance->ResAllocNode[Index].Alignment) + 1); BitsOfAlignment =
(UINTN)(HighBitSet64 (
RootBridgeInstance->ResAllocNode[Index].Alignment
) + 1);
switch (Index) { switch (Index) {
@ -395,8 +408,10 @@ NotifyPhase(
); );
if (!EFI_ERROR (Status)) { if (!EFI_ERROR (Status)) {
RootBridgeInstance->ResAllocNode[Index].Base = (UINTN)BaseAddress; RootBridgeInstance->ResAllocNode[Index].Base =
RootBridgeInstance->ResAllocNode[Index].Status = ResAllocated; (UINTN)BaseAddress;
RootBridgeInstance->ResAllocNode[Index].Status =
ResAllocated;
} else { } else {
ReturnStatus = Status; ReturnStatus = Status;
if (Status != EFI_OUT_OF_RESOURCES) { if (Status != EFI_OUT_OF_RESOURCES) {
@ -409,7 +424,8 @@ NotifyPhase(
case TypeMem32: case TypeMem32:
// //
// It is impossible for this chipset to align 0xFFFFFFFF for Mem32 // It is impossible for this chipset to align 0xFFFFFFFF for
// Mem32
// So clear it // So clear it
// //
@ -429,8 +445,10 @@ NotifyPhase(
if (!EFI_ERROR (Status)) { if (!EFI_ERROR (Status)) {
// We were able to allocate the PCI memory // We were able to allocate the PCI memory
RootBridgeInstance->ResAllocNode[Index].Base = (UINTN)BaseAddress; RootBridgeInstance->ResAllocNode[Index].Base =
RootBridgeInstance->ResAllocNode[Index].Status = ResAllocated; (UINTN)BaseAddress;
RootBridgeInstance->ResAllocNode[Index].Status =
ResAllocated;
} else { } else {
// Not able to allocate enough PCI memory // Not able to allocate enough PCI memory
@ -764,7 +782,10 @@ StartBusEnumeration(
// Program the Hardware(if needed) if error return EFI_DEVICE_ERROR // Program the Hardware(if needed) if error return EFI_DEVICE_ERROR
// //
Buffer = AllocatePool (sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof(EFI_ACPI_END_TAG_DESCRIPTOR)); Buffer = AllocatePool (
sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) +
sizeof(EFI_ACPI_END_TAG_DESCRIPTOR)
);
if (Buffer == NULL) { if (Buffer == NULL) {
return EFI_OUT_OF_RESOURCES; return EFI_OUT_OF_RESOURCES;
} }
@ -780,7 +801,8 @@ StartBusEnumeration(
((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrRangeMin = BusStart; ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrRangeMin = BusStart;
((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrRangeMax = 0; ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrRangeMax = 0;
((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrTranslationOffset = 0; ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrTranslationOffset = 0;
((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrLen = BusEnd - BusStart + 1; ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrLen =
BusEnd - BusStart + 1;
Temp = Temp + sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR); Temp = Temp + sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);
((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Desc = 0x79; ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Desc = 0x79;
@ -887,15 +909,19 @@ SetBusNumbers(
while (List != &HostBridgeInstance->Head) { while (List != &HostBridgeInstance->Head) {
RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List); RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
if (RootBridgeHandle == RootBridgeInstance->Handle) { if (RootBridgeHandle == RootBridgeInstance->Handle) {
BusStart = (UINTN)((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->AddrRangeMin; EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Desc;
BusLen = (UINTN)((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->AddrLen;
Desc = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr;
BusStart = (UINTN)Desc->AddrRangeMin;
BusLen = (UINTN)Desc->AddrLen;
BusEnd = BusStart + BusLen - 1; BusEnd = BusStart + BusLen - 1;
if (BusStart > BusEnd) { if (BusStart > BusEnd) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
if ((BusStart < RootBridgeInstance->BusBase) || (BusEnd > RootBridgeInstance->BusLimit)) { if ((BusStart < RootBridgeInstance->BusBase) ||
(BusEnd > RootBridgeInstance->BusLimit)) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
@ -1017,7 +1043,9 @@ SubmitResources(
// //
// Check address range alignment // Check address range alignment
// //
if (Ptr->AddrRangeMax >= 0xffffffff || Ptr->AddrRangeMax != (GetPowerOfTwo64 (Ptr->AddrRangeMax + 1) - 1)) { if (Ptr->AddrRangeMax >= 0xffffffff ||
Ptr->AddrRangeMax != (GetPowerOfTwo64 (
Ptr->AddrRangeMax + 1) - 1)) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
@ -1035,7 +1063,8 @@ SubmitResources(
// //
// check the memory resource request is supported by PCI root bridge // check the memory resource request is supported by PCI root bridge
// //
if (RootBridgeInstance->RootBridgeAttrib == EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM && if (RootBridgeInstance->RootBridgeAttrib ==
EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM &&
Ptr->SpecificFlag == 0x06) { Ptr->SpecificFlag == 0x06) {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
@ -1047,20 +1076,25 @@ SubmitResources(
// //
// Apply from GCD // Apply from GCD
// //
RootBridgeInstance->ResAllocNode[TypePMem32].Status = ResSubmitted; RootBridgeInstance->ResAllocNode[TypePMem32].Status =
ResSubmitted;
} else { } else {
RootBridgeInstance->ResAllocNode[TypeMem32].Length = AddrLen; RootBridgeInstance->ResAllocNode[TypeMem32].Length = AddrLen;
RootBridgeInstance->ResAllocNode[TypeMem32].Alignment = Alignment; RootBridgeInstance->ResAllocNode[TypeMem32].Alignment =
RootBridgeInstance->ResAllocNode[TypeMem32].Status = ResRequested; Alignment;
RootBridgeInstance->ResAllocNode[TypeMem32].Status =
ResRequested;
HostBridgeInstance->ResourceSubmited = TRUE; HostBridgeInstance->ResourceSubmited = TRUE;
} }
} }
if (Ptr->AddrSpaceGranularity == 64) { if (Ptr->AddrSpaceGranularity == 64) {
if (Ptr->SpecificFlag == 0x06) { if (Ptr->SpecificFlag == 0x06) {
RootBridgeInstance->ResAllocNode[TypePMem64].Status = ResSubmitted; RootBridgeInstance->ResAllocNode[TypePMem64].Status =
ResSubmitted;
} else { } else {
RootBridgeInstance->ResAllocNode[TypeMem64].Status = ResSubmitted; RootBridgeInstance->ResAllocNode[TypeMem64].Status =
ResSubmitted;
} }
} }
break; break;
@ -1164,7 +1198,10 @@ GetProposedResources(
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
Buffer = AllocateZeroPool (Number * sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof(EFI_ACPI_END_TAG_DESCRIPTOR)); Buffer = AllocateZeroPool (
Number * sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) +
sizeof(EFI_ACPI_END_TAG_DESCRIPTOR)
);
if (Buffer == NULL) { if (Buffer == NULL) {
return EFI_OUT_OF_RESOURCES; return EFI_OUT_OF_RESOURCES;
} }
@ -1188,8 +1225,9 @@ GetProposedResources(
Ptr->SpecificFlag = 0; Ptr->SpecificFlag = 0;
Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base; Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base;
Ptr->AddrRangeMax = 0; Ptr->AddrRangeMax = 0;
Ptr->AddrTranslationOffset = \ Ptr->AddrTranslationOffset = (ResStatus == ResAllocated) ?
(ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS; EFI_RESOURCE_SATISFIED :
EFI_RESOURCE_LESS;
Ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length; Ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;
break; break;
@ -1205,8 +1243,9 @@ GetProposedResources(
Ptr->AddrSpaceGranularity = 32; Ptr->AddrSpaceGranularity = 32;
Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base; Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base;
Ptr->AddrRangeMax = 0; Ptr->AddrRangeMax = 0;
Ptr->AddrTranslationOffset = \ Ptr->AddrTranslationOffset = (ResStatus == ResAllocated) ?
(ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS; EFI_RESOURCE_SATISFIED :
EFI_RESOURCE_LESS;
Ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length; Ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;
break; break;