mirror of https://github.com/acidanthera/audk.git
PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridge.c: rewrap code, strip trailing ws
In this patch the code and the comments embedded in code are rewrapped to 79 columns, plus any trailing whitespace is stripped. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Regression-tested-by: Gabriel Somlo <somlo@cmu.edu> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17948 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Laszlo Ersek
lersek
parent
7c7af556e0
commit
3d9eddb1b7
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@ -24,7 +24,9 @@
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//
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UINTN RootBridgeNumber[1] = { 1 };
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UINT64 RootBridgeAttribute[1][1] = { { EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM } };
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UINT64 RootBridgeAttribute[1][1] = {
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{ EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM }
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};
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EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[1][1] = {
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{
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@ -112,7 +114,8 @@ InitializePciHostBridge (
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// Create Host Bridge Device Handle
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//
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for (Loop1 = 0; Loop1 < HOST_BRIDGE_NUMBER; Loop1++) {
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HostBridge = AllocateCopyPool (sizeof(PCI_HOST_BRIDGE_INSTANCE), &mPciHostBridgeInstanceTemplate);
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HostBridge = AllocateCopyPool (sizeof(PCI_HOST_BRIDGE_INSTANCE),
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&mPciHostBridgeInstanceTemplate);
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if (HostBridge == NULL) {
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return EFI_OUT_OF_RESOURCES;
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}
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@ -122,7 +125,8 @@ InitializePciHostBridge (
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Status = gBS->InstallMultipleProtocolInterfaces (
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&HostBridge->HostBridgeHandle,
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&gEfiPciHostBridgeResourceAllocationProtocolGuid, &HostBridge->ResAlloc,
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&gEfiPciHostBridgeResourceAllocationProtocolGuid,
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&HostBridge->ResAlloc,
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NULL
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);
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if (EFI_ERROR (Status)) {
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@ -141,7 +145,8 @@ InitializePciHostBridge (
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}
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PrivateData->Signature = PCI_ROOT_BRIDGE_SIGNATURE;
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PrivateData->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[Loop1][Loop2];
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PrivateData->DevicePath =
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(EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[Loop1][Loop2];
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RootBridgeConstructor (
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&PrivateData->Io,
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@ -152,8 +157,10 @@ InitializePciHostBridge (
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Status = gBS->InstallMultipleProtocolInterfaces(
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&PrivateData->Handle,
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&gEfiDevicePathProtocolGuid, PrivateData->DevicePath,
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&gEfiPciRootBridgeIoProtocolGuid, &PrivateData->Io,
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&gEfiDevicePathProtocolGuid,
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PrivateData->DevicePath,
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&gEfiPciRootBridgeIoProtocolGuid,
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&PrivateData->Io,
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NULL
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);
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if (EFI_ERROR (Status)) {
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@ -334,21 +341,24 @@ NotifyPhase(
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case EfiPciHostBridgeBeginBusAllocation:
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//
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// No specific action is required here, can perform any chipset specific programing
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// No specific action is required here, can perform any chipset specific
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// programing
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//
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HostBridgeInstance->CanRestarted = FALSE;
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break;
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case EfiPciHostBridgeEndBusAllocation:
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//
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// No specific action is required here, can perform any chipset specific programing
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// No specific action is required here, can perform any chipset specific
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// programing
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//
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//HostBridgeInstance->CanRestarted = FALSE;
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break;
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case EfiPciHostBridgeBeginResourceAllocation:
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//
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// No specific action is required here, can perform any chipset specific programing
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// No specific action is required here, can perform any chipset specific
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// programing
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//
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//HostBridgeInstance->CanRestarted = FALSE;
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break;
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@ -371,7 +381,10 @@ NotifyPhase(
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//
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// Get the number of '1' in Alignment.
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//
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BitsOfAlignment = (UINTN) (HighBitSet64 (RootBridgeInstance->ResAllocNode[Index].Alignment) + 1);
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BitsOfAlignment =
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(UINTN)(HighBitSet64 (
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RootBridgeInstance->ResAllocNode[Index].Alignment
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) + 1);
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switch (Index) {
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@ -395,8 +408,10 @@ NotifyPhase(
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);
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if (!EFI_ERROR (Status)) {
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RootBridgeInstance->ResAllocNode[Index].Base = (UINTN)BaseAddress;
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RootBridgeInstance->ResAllocNode[Index].Status = ResAllocated;
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RootBridgeInstance->ResAllocNode[Index].Base =
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(UINTN)BaseAddress;
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RootBridgeInstance->ResAllocNode[Index].Status =
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ResAllocated;
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} else {
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ReturnStatus = Status;
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if (Status != EFI_OUT_OF_RESOURCES) {
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@ -409,7 +424,8 @@ NotifyPhase(
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case TypeMem32:
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//
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// It is impossible for this chipset to align 0xFFFFFFFF for Mem32
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// It is impossible for this chipset to align 0xFFFFFFFF for
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// Mem32
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// So clear it
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//
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@ -429,8 +445,10 @@ NotifyPhase(
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if (!EFI_ERROR (Status)) {
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// We were able to allocate the PCI memory
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RootBridgeInstance->ResAllocNode[Index].Base = (UINTN)BaseAddress;
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RootBridgeInstance->ResAllocNode[Index].Status = ResAllocated;
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RootBridgeInstance->ResAllocNode[Index].Base =
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(UINTN)BaseAddress;
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RootBridgeInstance->ResAllocNode[Index].Status =
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ResAllocated;
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} else {
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// Not able to allocate enough PCI memory
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@ -764,7 +782,10 @@ StartBusEnumeration(
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// Program the Hardware(if needed) if error return EFI_DEVICE_ERROR
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//
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Buffer = AllocatePool (sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof(EFI_ACPI_END_TAG_DESCRIPTOR));
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Buffer = AllocatePool (
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sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) +
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sizeof(EFI_ACPI_END_TAG_DESCRIPTOR)
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);
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if (Buffer == NULL) {
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return EFI_OUT_OF_RESOURCES;
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}
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@ -780,7 +801,8 @@ StartBusEnumeration(
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((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrRangeMin = BusStart;
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((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrRangeMax = 0;
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((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrTranslationOffset = 0;
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((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrLen = BusEnd - BusStart + 1;
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((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrLen =
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BusEnd - BusStart + 1;
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Temp = Temp + sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);
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((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Desc = 0x79;
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@ -887,15 +909,19 @@ SetBusNumbers(
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while (List != &HostBridgeInstance->Head) {
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RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
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if (RootBridgeHandle == RootBridgeInstance->Handle) {
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BusStart = (UINTN)((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->AddrRangeMin;
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BusLen = (UINTN)((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->AddrLen;
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EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Desc;
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Desc = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr;
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BusStart = (UINTN)Desc->AddrRangeMin;
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BusLen = (UINTN)Desc->AddrLen;
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BusEnd = BusStart + BusLen - 1;
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if (BusStart > BusEnd) {
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return EFI_INVALID_PARAMETER;
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}
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if ((BusStart < RootBridgeInstance->BusBase) || (BusEnd > RootBridgeInstance->BusLimit)) {
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if ((BusStart < RootBridgeInstance->BusBase) ||
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(BusEnd > RootBridgeInstance->BusLimit)) {
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return EFI_INVALID_PARAMETER;
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}
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@ -1017,7 +1043,9 @@ SubmitResources(
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//
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// Check address range alignment
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//
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if (Ptr->AddrRangeMax >= 0xffffffff || Ptr->AddrRangeMax != (GetPowerOfTwo64 (Ptr->AddrRangeMax + 1) - 1)) {
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if (Ptr->AddrRangeMax >= 0xffffffff ||
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Ptr->AddrRangeMax != (GetPowerOfTwo64 (
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Ptr->AddrRangeMax + 1) - 1)) {
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return EFI_INVALID_PARAMETER;
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}
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@ -1035,8 +1063,9 @@ SubmitResources(
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//
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// check the memory resource request is supported by PCI root bridge
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//
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if (RootBridgeInstance->RootBridgeAttrib == EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM &&
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Ptr->SpecificFlag == 0x06) {
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if (RootBridgeInstance->RootBridgeAttrib ==
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EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM &&
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Ptr->SpecificFlag == 0x06) {
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return EFI_INVALID_PARAMETER;
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}
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@ -1047,20 +1076,25 @@ SubmitResources(
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//
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// Apply from GCD
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//
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RootBridgeInstance->ResAllocNode[TypePMem32].Status = ResSubmitted;
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RootBridgeInstance->ResAllocNode[TypePMem32].Status =
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ResSubmitted;
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} else {
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RootBridgeInstance->ResAllocNode[TypeMem32].Length = AddrLen;
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RootBridgeInstance->ResAllocNode[TypeMem32].Alignment = Alignment;
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RootBridgeInstance->ResAllocNode[TypeMem32].Status = ResRequested;
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RootBridgeInstance->ResAllocNode[TypeMem32].Alignment =
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Alignment;
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RootBridgeInstance->ResAllocNode[TypeMem32].Status =
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ResRequested;
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HostBridgeInstance->ResourceSubmited = TRUE;
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}
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}
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if (Ptr->AddrSpaceGranularity == 64) {
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if (Ptr->SpecificFlag == 0x06) {
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RootBridgeInstance->ResAllocNode[TypePMem64].Status = ResSubmitted;
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RootBridgeInstance->ResAllocNode[TypePMem64].Status =
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ResSubmitted;
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} else {
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RootBridgeInstance->ResAllocNode[TypeMem64].Status = ResSubmitted;
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RootBridgeInstance->ResAllocNode[TypeMem64].Status =
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ResSubmitted;
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}
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}
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break;
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@ -1164,7 +1198,10 @@ GetProposedResources(
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return EFI_INVALID_PARAMETER;
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}
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Buffer = AllocateZeroPool (Number * sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof(EFI_ACPI_END_TAG_DESCRIPTOR));
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Buffer = AllocateZeroPool (
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Number * sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) +
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sizeof(EFI_ACPI_END_TAG_DESCRIPTOR)
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);
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if (Buffer == NULL) {
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return EFI_OUT_OF_RESOURCES;
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}
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@ -1188,8 +1225,9 @@ GetProposedResources(
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Ptr->SpecificFlag = 0;
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Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base;
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Ptr->AddrRangeMax = 0;
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Ptr->AddrTranslationOffset = \
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(ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
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Ptr->AddrTranslationOffset = (ResStatus == ResAllocated) ?
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EFI_RESOURCE_SATISFIED :
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EFI_RESOURCE_LESS;
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Ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;
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break;
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@ -1205,8 +1243,9 @@ GetProposedResources(
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Ptr->AddrSpaceGranularity = 32;
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Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base;
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Ptr->AddrRangeMax = 0;
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Ptr->AddrTranslationOffset = \
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(ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
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Ptr->AddrTranslationOffset = (ResStatus == ResAllocated) ?
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EFI_RESOURCE_SATISFIED :
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EFI_RESOURCE_LESS;
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Ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;
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break;
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@ -1322,10 +1361,10 @@ GetProposedResources(
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EFI_STATUS
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EFIAPI
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PreprocessController (
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IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
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IN EFI_HANDLE RootBridgeHandle,
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,
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IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase
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IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
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IN EFI_HANDLE RootBridgeHandle,
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IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,
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IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase
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)
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{
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PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
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