mirror of https://github.com/acidanthera/audk.git
Remove hard code value and create new PCDs for OpROM reserved range in CSM module.
Signed-off-by: Li Elvin <elvin.li@intel.com> Reviewed-by: Yao Jiewen <jiewen.yao@intel.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13991 6f19259b-4bc3-4df7-8a09-765794883524
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@ -682,6 +682,7 @@ LegacyBiosInstall (
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LEGACY_BIOS_INSTANCE *Private;
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EFI_TO_COMPATIBILITY16_INIT_TABLE *EfiToLegacy16InitTable;
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EFI_PHYSICAL_ADDRESS MemoryAddress;
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EFI_PHYSICAL_ADDRESS EbdaReservedBaseAddress;
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VOID *MemoryPtr;
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EFI_PHYSICAL_ADDRESS MemoryAddressUnder1MB;
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UINTN Index;
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@ -880,9 +881,21 @@ LegacyBiosInstall (
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//
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// Allocate all 32k chunks from 0x60000 ~ 0x88000 for Legacy OPROMs that
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// don't use PMM but look for zeroed memory. Note that various non-BBS
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// SCSIs expect different areas to be free
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// OpROMs expect different areas to be free
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//
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for (MemStart = 0x60000; MemStart < 0x88000; MemStart += 0x1000) {
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EbdaReservedBaseAddress = MemoryAddress;
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MemoryAddress = PcdGet32 (PcdOpromReservedMemoryBase);
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MemorySize = PcdGet32 (PcdOpromReservedMemorySize);
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//
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// Check if base address and size for reserved memory are 4KB aligned.
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//
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ASSERT ((MemoryAddress & 0xFFF) == 0);
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ASSERT ((MemorySize & 0xFFF) == 0);
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//
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// Check if the reserved memory is below EBDA reserved range.
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//
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ASSERT ((MemoryAddress < EbdaReservedBaseAddress) && ((MemoryAddress + MemorySize - 1) < EbdaReservedBaseAddress));
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for (MemStart = MemoryAddress; MemStart < MemoryAddress + MemorySize; MemStart += 0x1000) {
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Status = AllocateLegacyMemory (
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AllocateAddress,
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MemStart,
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@ -140,6 +140,8 @@
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gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdEndOpromShadowAddress
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gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLowPmmMemorySize
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gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdHighPmmMemorySize
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gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdOpromReservedMemoryBase
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gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdOpromReservedMemorySize
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[Depex]
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gEfiLegacyRegion2ProtocolGuid AND gEfiLegacyInterruptProtocolGuid AND gEfiLegacyBiosPlatformProtocolGuid AND gEfiLegacy8259ProtocolGuid AND gEfiGenericMemTestProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid
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@ -199,6 +199,18 @@
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## The value should be a multiple of 4KB.
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gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdEbdaReservedMemorySize|0x8000|UINT32|0x30000005
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## The PCD is used to specify memory base address for OPROM to find free memory.
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# Some OPROMs do not use EBDA or PMM to allocate memory for its usage,
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# instead they find the memory filled with zero from 0x20000.
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# The range should be below the EBDA reserved range from
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# (CONVENTIONAL_MEMORY_TOP - PcdEbdaReservedMemorySize) to CONVENTIONAL_MEMORY_TOP.
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gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdOpromReservedMemoryBase|0x60000|UINT32|0x3000000c
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## The PCD is used to specify memory size with bytes for OPROM to find free memory.
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## The value should be a multiple of 4KB. And the range should be below the EBDA reserved range from
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# (CONVENTIONAL_MEMORY_TOP - PcdEbdaReservedMemorySize) to CONVENTIONAL_MEMORY_TOP.
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gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdOpromReservedMemorySize|0x28000|UINT32|0x3000000d
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## The PCD is used to specify memory size with page number for a pre-allocated reserved memory to be used
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# by PEI in S3 phase. The default size 32K. When changing the value of this PCD, the platform
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# developer should make sure the memory size is large enough to meet PEI requiremnt in S3 phase.
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