mirror of https://github.com/acidanthera/audk.git
ArmPlatformPkg/ArmVExpressLibRTSM: Removed unused dead code
This code is only specific to the ARM Versatile Express hardware board. There is no concept of logic tile on the FVP model. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15460 6f19259b-4bc3-4df7-8a09-765794883524
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@ -1,6 +1,6 @@
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/** @file
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*
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* Copyright (c) 2011, ARM Limited. All rights reserved.
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* Copyright (c) 2011-2014, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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@ -19,7 +19,7 @@
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#include <Library/MemoryAllocationLib.h>
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#include <ArmPlatform.h>
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// Number of Virtual Memory Map Descriptors without a Logic Tile
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// Number of Virtual Memory Map Descriptors
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#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 5
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// DDR attributes
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@ -105,19 +105,6 @@ ArmPlatformGetVirtualMemoryMap (
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VirtualMemoryTable[Index].Length = 2 * ARM_VE_SMB_PERIPH_SZ;
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VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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//TODO:This should be enabled for final release. Right now, ARM VE RTSM crashes.
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// // If a Logic Tile is connected to The ARM Versatile Express Motherboard
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// if (MmioRead32(ARM_VE_SYS_PROCID1_REG) != 0) {
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// VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_EXT_AXI_BASE;
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// VirtualMemoryTable[Index].VirtualBase = ARM_VE_EXT_AXI_BASE;
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// VirtualMemoryTable[Index].Length = ARM_VE_EXT_AXI_SZ;
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// VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
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//
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// ASSERT((Index + 1) == (MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS + 1));
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// } else {
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// ASSERT((Index + 1) == MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
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// }
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// End of Table
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VirtualMemoryTable[++Index].PhysicalBase = 0;
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VirtualMemoryTable[Index].VirtualBase = 0;
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