mirror of https://github.com/acidanthera/audk.git
ArmPlatformPkg: Removed the 'Identify' functions
This function was introduced in some drivers to check if the ARM controller was present in the memory map. It was using a 8 bit access to get the value from the Identification registers. These accesses could generate access error on some buses. Instead of replacing the 8bit access by a 32bit access, these fcuntions have been removed because they are only useful when the boot firmware is ported on a new platform. Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13247 6f19259b-4bc3-4df7-8a09-765794883524
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@ -1,6 +1,7 @@
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/** @file PL111Lcd.c
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Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>
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Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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@ -25,43 +26,11 @@
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*
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**********************************************************************/
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EFI_STATUS
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PL111Indentify (
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VOID
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)
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{
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// Check if this is a PrimeCell Peripheral
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if ( ( MmioRead8( PL111_REG_CLCD_P_CELL_ID_0 ) != 0x0D )
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|| ( MmioRead8( PL111_REG_CLCD_P_CELL_ID_1 ) != 0xF0 )
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|| ( MmioRead8( PL111_REG_CLCD_P_CELL_ID_2 ) != 0x05 )
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|| ( MmioRead8( PL111_REG_CLCD_P_CELL_ID_3 ) != 0xB1 ) ) {
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return EFI_NOT_FOUND;
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}
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// Check if this PrimeCell Peripheral is the PL111 LCD
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if ( ( MmioRead8( PL111_REG_CLCD_PERIPH_ID_0 ) != 0x11 )
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|| ( MmioRead8( PL111_REG_CLCD_PERIPH_ID_1 ) != 0x11 )
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|| ( (MmioRead8( PL111_REG_CLCD_PERIPH_ID_2 ) & 0xF) != 0x04 )
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|| ( MmioRead8( PL111_REG_CLCD_PERIPH_ID_3 ) != 0x00 ) ) {
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return EFI_NOT_FOUND;
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}
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return EFI_SUCCESS;
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}
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EFI_STATUS
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LcdInitialize (
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IN EFI_PHYSICAL_ADDRESS VramBaseAddress
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)
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{
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EFI_STATUS Status = EFI_SUCCESS;
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// Check if the PL111 is fitted on this motherboard
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Status = PL111Indentify ();
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if (EFI_ERROR( Status )) {
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return EFI_DEVICE_ERROR;
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}
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// Define start of the VRAM. This never changes for any graphics mode
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MmioWrite32(PL111_REG_LCD_UP_BASE, (UINT32) VramBaseAddress);
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MmioWrite32(PL111_REG_LCD_LP_BASE, 0); // We are not using a double buffer
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@ -29,30 +29,6 @@
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EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;
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EFI_STATUS
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SP805Identify (
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VOID
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)
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{
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// Check if this is a PrimeCell Peripheral
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if ( (MmioRead8 (SP805_WDOG_PCELL_ID0) != 0x0D)
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|| (MmioRead8 (SP805_WDOG_PCELL_ID1) != 0xF0)
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|| (MmioRead8 (SP805_WDOG_PCELL_ID2) != 0x05)
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|| (MmioRead8 (SP805_WDOG_PCELL_ID3) != 0xB1)) {
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return EFI_NOT_FOUND;
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}
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// Check if this PrimeCell Peripheral is the SP805 Watchdog Timer
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if ( (MmioRead8 (SP805_WDOG_PERIPH_ID0) != 0x05)
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|| (MmioRead8 (SP805_WDOG_PERIPH_ID1) != 0x18)
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|| ((MmioRead8 (SP805_WDOG_PERIPH_ID2) & 0x0000000F) != 0x04)
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|| (MmioRead8 (SP805_WDOG_PERIPH_ID3) != 0x00)) {
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return EFI_NOT_FOUND;
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}
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return EFI_SUCCESS;
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}
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/**
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Make sure the SP805 registers are unlocked for writing.
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@ -363,13 +339,6 @@ SP805Initialize (
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EFI_STATUS Status;
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EFI_HANDLE Handle;
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// Check if the SP805 hardware watchdog module exists on board
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Status = SP805Identify();
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if (EFI_ERROR(Status)) {
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Status = EFI_DEVICE_ERROR;
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goto EXIT;
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}
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// Unlock access to the SP805 registers
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SP805Unlock ();
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@ -409,7 +378,7 @@ SP805Initialize (
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goto EXIT;
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}
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EXIT:
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EXIT:
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if(EFI_ERROR(Status)) {
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// The watchdog failed to initialize
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ASSERT(FALSE);
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