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MdePkg/BaseCpuLib: RISC-V Base CPU library

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implementation.

Implement RISC-V CPU related functions in BaseCpuLib.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2672

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
This commit is contained in:
Abner Chang 2020-04-07 15:59:20 +08:00 committed by mergify[bot]
parent 54a3d5ec48
commit 3fd8800954
3 changed files with 27 additions and 3 deletions
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6
MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
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@ -7,6 +7,7 @@
# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR> # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR> # Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
# #
# SPDX-License-Identifier: BSD-2-Clause-Patent # SPDX-License-Identifier: BSD-2-Clause-Patent
# #
@ -24,7 +25,7 @@
# #
# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 # VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64
# #
[Sources.IA32] [Sources.IA32]
@ -59,6 +60,9 @@
AArch64/CpuFlushTlb.asm | MSFT AArch64/CpuFlushTlb.asm | MSFT
AArch64/CpuSleep.asm | MSFT AArch64/CpuSleep.asm | MSFT
[Sources.RISCV64]
RiscV/Cpu.S
[Packages] [Packages]
MdePkg/MdePkg.dec MdePkg/MdePkg.dec

5
MdePkg/Library/BaseCpuLib/BaseCpuLib.uni
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@ -1,12 +1,13 @@
// /** @file // /** @file
// Instance of CPU Library for various architecture. // Instance of CPU Library for various architecture.
// //
// CPU Library implemented using ASM functions for IA-32 and X64, // CPU Library implemented using ASM functions for IA-32, X64 and RISCV64,
// PAL CALLs for IPF, and empty functions for EBC. // PAL CALLs for IPF, and empty functions for EBC.
// //
// Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR> // Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
// Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> // Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
// Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR> // Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
// //
// SPDX-License-Identifier: BSD-2-Clause-Patent // SPDX-License-Identifier: BSD-2-Clause-Patent
// //
@ -15,5 +16,5 @@
#string STR_MODULE_ABSTRACT #language en-US "Instance of CPU Library for various architectures" #string STR_MODULE_ABSTRACT #language en-US "Instance of CPU Library for various architectures"
#string STR_MODULE_DESCRIPTION #language en-US "CPU Library implemented using ASM functions for IA-32 and X64, PAL CALLs for IPF, and empty functions for EBC." #string STR_MODULE_DESCRIPTION #language en-US "CPU Library implemented using ASM functions for IA-32, X64 and RISCV64, PAL CALLs for IPF, and empty functions for EBC."

19
MdePkg/Library/BaseCpuLib/RiscV/Cpu.S Normal file
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@ -0,0 +1,19 @@
//------------------------------------------------------------------------------
//
// CpuSleep for RISC-V
//
// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
//------------------------------------------------------------------------------
.data
.align 3
.section .text
.global ASM_PFX(_CpuSleep)
ASM_PFX(_CpuSleep):
wfi
ret