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Fix the SMRAM caching range base and size. The original code uses the biggest SMRAM range base and size to set the cache attribute by gDS->SetMemorySpaceAttributes(). This is not correct because the platform code might split the TSEG into several ranges. The fix searches and joins all the adjacent ranges to the biggest SMRAM range into a cacheable range so that TSEG can be cached as a whole.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10213 6f19259b-4bc3-4df7-8a09-765794883524
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@ -227,6 +227,8 @@ EFI_SMM_CONTROL2_PROTOCOL *mSmmControl2;
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EFI_SMM_ACCESS2_PROTOCOL *mSmmAccess;
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EFI_SMM_ACCESS2_PROTOCOL *mSmmAccess;
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EFI_SMRAM_DESCRIPTOR *mCurrentSmramRange;
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EFI_SMRAM_DESCRIPTOR *mCurrentSmramRange;
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BOOLEAN mSmmLocked = FALSE;
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BOOLEAN mSmmLocked = FALSE;
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EFI_PHYSICAL_ADDRESS mSmramCacheBase;
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UINT64 mSmramCacheSize;
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//
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//
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// Table of Protocol notification and GUIDed Event notifications that the SMM IPL requires
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// Table of Protocol notification and GUIDed Event notifications that the SMM IPL requires
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@ -272,6 +274,49 @@ SMM_IPL_EVENT_NOTIFICATION mSmmIplEvents[] = {
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{ FALSE, FALSE, NULL, NULL, NULL, NULL }
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{ FALSE, FALSE, NULL, NULL, NULL, NULL }
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};
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};
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/**
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Find the maximum SMRAM cache range that covers the range specified by SmramRange.
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This function searches and joins all adjacent ranges of SmramRange into a range to be cached.
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@param SmramRange The SMRAM range to search from.
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@param SmramCacheBase The returned cache range base.
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@param SmramCacheSize The returned cache range size.
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**/
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VOID
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GetSmramCacheRange (
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IN EFI_SMRAM_DESCRIPTOR *SmramRange,
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OUT EFI_PHYSICAL_ADDRESS *SmramCacheBase,
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OUT UINT64 *SmramCacheSize
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)
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{
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UINTN Index;
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EFI_PHYSICAL_ADDRESS RangeCpuStart;
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UINT64 RangePhysicalSize;
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BOOLEAN FoundAjacentRange;
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*SmramCacheBase = SmramRange->CpuStart;
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*SmramCacheSize = SmramRange->PhysicalSize;
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do {
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FoundAjacentRange = FALSE;
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for (Index = 0; Index < gSmmCorePrivate->SmramRangeCount; Index++) {
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RangeCpuStart = gSmmCorePrivate->SmramRanges[Index].CpuStart;
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RangePhysicalSize = gSmmCorePrivate->SmramRanges[Index].PhysicalSize;
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if (RangeCpuStart < *SmramCacheBase && *SmramCacheBase == (RangeCpuStart + RangePhysicalSize)) {
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*SmramCacheBase = RangeCpuStart;
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*SmramCacheSize += RangePhysicalSize;
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FoundAjacentRange = TRUE;
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} else if ((*SmramCacheBase + *SmramCacheSize) == RangeCpuStart && RangePhysicalSize > 0) {
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*SmramCacheSize += RangePhysicalSize;
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FoundAjacentRange = TRUE;
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}
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}
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} while (FoundAjacentRange);
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}
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/**
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/**
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Indicate whether the driver is currently executing in the SMM Initialization phase.
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Indicate whether the driver is currently executing in the SMM Initialization phase.
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@ -515,8 +560,8 @@ SmmIplSmmConfigurationEventNotify (
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// Attempt to reset SMRAM cacheability to UC
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// Attempt to reset SMRAM cacheability to UC
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//
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//
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Status = gDS->SetMemorySpaceAttributes(
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Status = gDS->SetMemorySpaceAttributes(
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mCurrentSmramRange->CpuStart,
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mSmramCacheBase,
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mCurrentSmramRange->PhysicalSize,
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mSmramCacheSize,
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EFI_MEMORY_UC
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EFI_MEMORY_UC
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);
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);
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if (EFI_ERROR (Status)) {
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if (EFI_ERROR (Status)) {
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@ -1076,12 +1121,13 @@ SmmIplEntry (
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(VOID *)(UINTN)(mCurrentSmramRange->CpuStart + mCurrentSmramRange->PhysicalSize - 1)
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(VOID *)(UINTN)(mCurrentSmramRange->CpuStart + mCurrentSmramRange->PhysicalSize - 1)
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));
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));
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GetSmramCacheRange (mCurrentSmramRange, &mSmramCacheBase, &mSmramCacheSize);
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//
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//
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// Attempt to set SMRAM cacheability to WB
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// Attempt to set SMRAM cacheability to WB
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//
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//
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Status = gDS->SetMemorySpaceAttributes(
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Status = gDS->SetMemorySpaceAttributes(
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mCurrentSmramRange->CpuStart,
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mSmramCacheBase,
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mCurrentSmramRange->PhysicalSize,
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mSmramCacheSize,
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EFI_MEMORY_WB
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EFI_MEMORY_WB
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);
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);
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if (EFI_ERROR (Status)) {
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if (EFI_ERROR (Status)) {
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@ -1129,8 +1175,8 @@ SmmIplEntry (
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// Attempt to reset SMRAM cacheability to UC
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// Attempt to reset SMRAM cacheability to UC
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//
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//
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Status = gDS->SetMemorySpaceAttributes(
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Status = gDS->SetMemorySpaceAttributes(
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mCurrentSmramRange->CpuStart,
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mSmramCacheBase,
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mCurrentSmramRange->PhysicalSize,
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mSmramCacheSize,
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EFI_MEMORY_UC
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EFI_MEMORY_UC
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);
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);
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if (EFI_ERROR (Status)) {
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if (EFI_ERROR (Status)) {
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