tyler.durden
/
audk
mirror of https://github.com/acidanthera/audk.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Update IndustryStandard according to code review comments. 

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@6155 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
xli24 2008-10-20 15:16:32 +00:00
parent ee256e2c4d
commit 4135253bde
10 changed files with 1292 additions and 871 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

514
MdePkg/Include/IndustryStandard/Sal.h
View File

@ -1,7 +1,8 @@
/** @file
Main SAL API's defined in SAL 3.0 specification.
Main SAL API's defined in Intel Itanium Processor Family System Abstraction
Layer Specification Revision 3.2 (December 2003)
Copyright (c) 2006, Intel Corporation
Copyright (c) 2006 - 2008, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -16,89 +17,170 @@
#define __SAL_API_H__
///
/// FIT Types
/// Table 2-2 of Intel Itanium Processor Family System Abstraction Layer Specification December 2003
///
#define EFI_SAL_FIT_FIT_HEADER_TYPE 0x00
#define EFI_SAL_FIT_PAL_B_TYPE 0x01
///
/// type from 0x02 to 0x0E is reserved.
///
#define EFI_SAL_FIT_PAL_A_TYPE 0x0F
///
/// OEM-defined type range is from 0x10 to 0x7E. Here we defined the PEI_CORE type as 0x10
///
#define EFI_SAL_FIT_PEI_CORE_TYPE 0x10
#define EFI_SAL_FIT_UNUSED_TYPE 0x7F
///
/// EFI_SAL_STATUS
/// SAL return status type
///
typedef UINTN EFI_SAL_STATUS;
///
/// Call completed without error.
///
#define EFI_SAL_SUCCESS ((EFI_SAL_STATUS) 0)
///
/// Call completed without error but some information was lost due to overflow.
///
#define EFI_SAL_OVERFLOW ((EFI_SAL_STATUS) 1)
///
/// Call completed without error; effect a warm boot of the system to complete the update.
///
#define EFI_SAL_WARM_BOOT_NEEDED ((EFI_SAL_STATUS) 2)
///
/// More information is available for retrieval.
///
#define EFI_SAL_MORE_RECORDS ((EFI_SAL_STATUS) 3)
///
/// Not implemented.
///
#define EFI_SAL_NOT_IMPLEMENTED ((EFI_SAL_STATUS) - 1)
///
/// Invalid Argument.
///
#define EFI_SAL_INVALID_ARGUMENT ((EFI_SAL_STATUS) - 2)
///
/// Call completed without error.
///
#define EFI_SAL_ERROR ((EFI_SAL_STATUS) - 3)
///
/// Virtual address not registered.
///
#define EFI_SAL_VIRTUAL_ADDRESS_ERROR ((EFI_SAL_STATUS) - 4)
///
/// No information available.
///
#define EFI_SAL_NO_INFORMATION ((EFI_SAL_STATUS) - 5)
///
/// Scratch buffer required.
///
#define EFI_SAL_NOT_ENOUGH_SCRATCH ((EFI_SAL_STATUS) - 9)
//
// Return values from SAL
//
///
/// Return registers from SAL
///
typedef struct {
EFI_SAL_STATUS Status; // register r8
///
/// SAL return status value in r8
///
EFI_SAL_STATUS Status;
///
/// SAL returned value in r9
///
UINTN r9;
///
/// SAL returned value in r10
///
UINTN r10;
///
/// SAL returned value in r11
///
UINTN r11;
} SAL_RETURN_REGS;
///
/// Delivery Mode of IPF CPU.
///
typedef enum {
EFI_DELIVERY_MODE_INT,
EFI_DELIVERY_MODE_MPreserved1,
EFI_DELIVERY_MODE_PMI,
EFI_DELIVERY_MODE_MPreserved2,
EFI_DELIVERY_MODE_NMI,
EFI_DELIVERY_MODE_INIT,
EFI_DELIVERY_MODE_MPreserved3,
EFI_DELIVERY_MODE_ExtINT
} EFI_DELIVERY_MODE;
/**
Prototype of SAL procedures.
typedef SAL_RETURN_REGS (EFIAPI *SAL_PROC)
(
IN UINT64 FunctionId,
IN UINT64 Arg2,
IN UINT64 Arg3,
IN UINT64 Arg4,
IN UINT64 Arg5,
IN UINT64 Arg6,
IN UINT64 Arg7,
IN UINT64 Arg8
@param Arg0 Functional identifier.
The upper 32 bits are ignored and only the lower 32 bits
are used. The following functional identifiers are defined:
0x01XXXXXX – Architected SAL functional group.
0x02XXXXXX to 0x03XXXXXX – OEM SAL functional group. Each OEM is
allowed to use the entire range in the 0x02XXXXXX to 0x03XXXXXX range.
0x04XXXXXX to 0xFFFFFFFF – Reserved.
@param Arg1 The first parameter of the architected/OEM specific SAL functions.
@param Arg2 The second parameter of the architected/OEM specific SAL functions.
@param Arg3 The third parameter passed to the ESAL function based
@param Arg4 The fourth parameter passed to the ESAL function based
@param Arg5 The fifth parameter passed to the ESAL function based
@param Arg6 The sixth parameter passed to the ESAL function
@param Arg7 The seventh parameter passed to the ESAL function based
@return r8 Return status: positive number indicates successful,
negative number indicates failure.
r9 Other return parameter in r9.
r10 Other return parameter in r10.
r11 Other return parameter in r11.
**/
typedef
SAL_RETURN_REGS
(EFIAPI *SAL_PROC) (
IN UINT64 FunctionId,
IN UINT64 Arg2,
IN UINT64 Arg3,
IN UINT64 Arg4,
IN UINT64 Arg5,
IN UINT64 Arg6,
IN UINT64 Arg7,
IN UINT64 Arg8
);
//
// SAL Procedure FunctionId definition
//
///
/// Register software code locations with SAL.
///
#define EFI_SAL_SET_VECTORS 0x01000000
///
/// Return Machine State information obtained by SAL.
///
#define EFI_SAL_GET_STATE_INFO 0x01000001
///
/// Obtain size of Machine State information.
///
#define EFI_SAL_GET_STATE_INFO_SIZE 0x01000002
///
/// Clear Machine State information.
///
#define EFI_SAL_CLEAR_STATE_INFO 0x01000003
///
/// Cause the processor to go into a spin loop within SAL.
///
#define EFI_SAL_MC_RENDEZ 0x01000004
///
/// Register the machine check interface layer with SAL.
///
#define EFI_SAL_MC_SET_PARAMS 0x01000005
///
/// Register the physical addresses of locations needed by SAL.
///
#define EFI_SAL_REGISTER_PHYSICAL_ADDR 0x01000006
///
/// Flush the instruction or data caches.
///
#define EFI_SAL_CACHE_FLUSH 0x01000008
///
/// Initialize the instruction and data caches.
///
#define EFI_SAL_CACHE_INIT 0x01000009
///
/// Read from the PCI configuration space.
///
#define EFI_SAL_PCI_CONFIG_READ 0x01000010
///
/// Write to the PCI configuration space.
///
#define EFI_SAL_PCI_CONFIG_WRITE 0x01000011
///
/// Return the base frequency of the platform.
///
#define EFI_SAL_FREQ_BASE 0x01000012
///
/// Returns information on the physical processor mapping within the platform.
///
#define EFI_SAL_PHYSICAL_ID_INFO 0x01000013
///
/// Update the contents of firmware blocks.
///
#define EFI_SAL_UPDATE_PAL 0x01000020
#define EFI_SAL_FUNCTION_ID_MASK 0x0000ffff
@ -109,12 +191,18 @@ typedef SAL_RETURN_REGS (EFIAPI *SAL_PROC)
// Not much point in using typedefs or enums because all params
// are UINT64 and the entry point is common
//
// EFI_SAL_SET_VECTORS
//
// Parameter of EFI_SAL_SET_VECTORS
//
// Vector type
//
#define EFI_SAL_SET_MCA_VECTOR 0x0
#define EFI_SAL_SET_INIT_VECTOR 0x1
#define EFI_SAL_SET_BOOT_RENDEZ_VECTOR 0x2
///
/// Format of length_cs_n argument.
///
typedef struct {
UINT64 Length : 32;
UINT64 ChecksumValid : 1;
@ -124,8 +212,9 @@ typedef struct {
} SAL_SET_VECTORS_CS_N;
//
// EFI_SAL_GET_STATE_INFO, EFI_SAL_GET_STATE_INFO_SIZE,
// EFI_SAL_CLEAR_STATE_INFO
// Parameter of EFI_SAL_GET_STATE_INFO, EFI_SAL_GET_STATE_INFO_SIZE, and EFI_SAL_CLEAR_STATE_INFO
//
// Type of information
//
#define EFI_SAL_MCA_STATE_INFO 0x0
#define EFI_SAL_INIT_STATE_INFO 0x1
@ -133,22 +222,31 @@ typedef struct {
#define EFI_SAL_CP_STATE_INFO 0x3
//
// EFI_SAL_MC_SET_PARAMS
// Parameter of EFI_SAL_MC_SET_PARAMS
//
// Unsigned 64-bit integer value for the parameter type of the machine check interface
//
#define EFI_SAL_MC_SET_RENDEZ_PARAM 0x1
#define EFI_SAL_MC_SET_WAKEUP_PARAM 0x2
#define EFI_SAL_MC_SET_CPE_PARAM 0x3
//
// Unsigned 64-bit integer value indicating whether interrupt vector or
// memory address is specified
//
#define EFI_SAL_MC_SET_INTR_PARAM 0x1
#define EFI_SAL_MC_SET_MEM_PARAM 0x2
//
// EFI_SAL_REGISTER_PAL_PHYSICAL_ADDR
// Parameter of EFI_SAL_REGISTER_PAL_PHYSICAL_ADDR
//
// The encoded value of the entity whose physical address is registered
//
#define EFI_SAL_REGISTER_PAL_ADDR 0x0
//
// EFI_SAL_CACHE_FLUSH
// Parameter of EFI_SAL_CACHE_FLUSH
//
// Unsigned 64-bit integer denoting type of cache flush operation
//
#define EFI_SAL_FLUSH_I_CACHE 0x01
#define EFI_SAL_FLUSH_D_CACHE 0x02
@ -156,12 +254,21 @@ typedef struct {
#define EFI_SAL_FLUSH_MAKE_COHERENT 0x04
//
// EFI_SAL_PCI_CONFIG_READ, EFI_SAL_PCI_CONFIG_WRITE
// Parameter of EFI_SAL_PCI_CONFIG_READ and EFI_SAL_PCI_CONFIG_WRITE
//
// PCI config size
//
#define EFI_SAL_PCI_CONFIG_ONE_BYTE 0x1
#define EFI_SAL_PCI_CONFIG_TWO_BYTES 0x2
#define EFI_SAL_PCI_CONFIG_FOUR_BYTES 0x4
//
// The type of PCI configuration address
//
#define EFI_SAL_PCI_COMPATIBLE_ADDRESS 0x0
#define EFI_SAL_PCI_EXTENDED_REGISTER_ADDRESS 0x1
///
/// Format of PCI Compatible Address
///
typedef struct {
UINT64 Register : 8;
UINT64 Function : 3;
@ -170,16 +277,34 @@ typedef struct {
UINT64 Segment : 8;
UINT64 Reserved : 32;
} SAL_PCI_ADDRESS;
///
/// Format of Extended Register Address
///
typedef struct {
UINT64 Register : 8;
UINT64 ExtendedRegister : 4;
UINT64 Function : 3;
UINT64 Device : 5;
UINT64 Bus : 8;
UINT64 Segment : 16;
UINT64 Reserved : 20;
} SAL_PCI_EXTENDED_REGISTER_ADDRESS;
//
// EFI_SAL_FREQ_BASE
// Parameter of EFI_SAL_FREQ_BASE
//
// Unsigned 64-bit integer specifying the type of clock source
//
#define EFI_SAL_CPU_INPUT_FREQ_BASE 0x0
#define EFI_SAL_PLATFORM_IT_FREQ_BASE 0x1
#define EFI_SAL_PLATFORM_RTC_FREQ_BASE 0x2
//
// EFI_SAL_UPDATE_PAL
// Parameter and return value of EFI_SAL_UPDATE_PAL
//
// Return parameter provides additional information on the
// failure when the status field contains a value of –3,
// returned in r9.
//
#define EFI_SAL_UPDATE_BAD_PAL_VERSION ((UINT64) -1)
#define EFI_SAL_UPDATE_PAL_AUTH_FAIL ((UINT64) -2)
@ -189,7 +314,9 @@ typedef struct {
#define EFI_SAL_UPDATE_PAL_ERASE_FAIL ((UINT64) -11)
#define EFI_SAL_UPDATE_PAL_READ_FAIL ((UINT64) -12)
#define EFI_SAL_UPDATE_PAL_CANT_FIT ((UINT64) -13)
///
/// 64-byte header of update data block.
///
typedef struct {
UINT32 Size;
UINT32 MmddyyyyDate;
@ -198,7 +325,12 @@ typedef struct {
UINT8 Reserved[5];
UINT64 FwVendorId;
} SAL_UPDATE_PAL_DATA_BLOCK;
///
/// Data structure pointed by parameter param_buf.
/// It is a 16-byte aligned data structure in memory with a length of 32 bytes
/// that describes the new firmware. This information is organized in the form
/// of a linked list with each element describing one firmware component.
///
typedef struct _SAL_UPDATE_PAL_INFO_BLOCK {
struct _SAL_UPDATE_PAL_INFO_BLOCK *Next;
struct SAL_UPDATE_PAL_DATA_BLOCK *DataBlock;
@ -206,27 +338,64 @@ typedef struct _SAL_UPDATE_PAL_INFO_BLOCK {
UINT8 Reserved[15];
} SAL_UPDATE_PAL_INFO_BLOCK;
//
// SAL System Table Definitions
//
///
/// SAL System Table Definitions
///
#pragma pack(1)
typedef struct {
///
/// The ASCII string representation of “SST_”, which confirms the presence of the table.
///
UINT32 Signature;
///
/// The length of the entire table in bytes, starting from offset zero and including the
/// header and all entries indicated by the EntryCount field.
///
UINT32 Length;
///
/// The revision number of the Itanium Processor Family System Abstraction Layer
/// Specification supported by the SAL implementation in binary coded decimal (BCD) format.
///
UINT16 SalRevision;
///
/// The number of entries in the variable portion of the table.
///
UINT16 EntryCount;
///
/// A modulo checksum of the entire table and the entries following this table.
///
UINT8 CheckSum;
///
/// Unused, must be zero.
///
UINT8 Reserved[7];
///
/// Version Number of the SAL_A firmware implementation in BCD format.
///
UINT16 SalAVersion;
///
/// Version Number of the SAL_B firmware implementation in BCD format.
///
UINT16 SalBVersion;
///
/// An ASCII identification string which uniquely identifies the manufacturer
/// of the system hardware.
///
UINT8 OemId[32];
///
/// An ASCII identification string which uniquely identifies a family of
/// compatible products from the manufacturer.
///
UINT8 ProductId[32];
///
/// Unused, must be zero.
///
UINT8 Reserved2[8];
} SAL_SYSTEM_TABLE_HEADER;
#pragma pack()
#define EFI_SAL_ST_HEADER_SIGNATURE "SST_"
#define EFI_SAL_REVISION 0x0300
#define EFI_SAL_REVISION 0x0320
//
// SAL System Types
//
@ -248,8 +417,11 @@ typedef struct {
#define EFI_SAL_ST_AP_WAKEUP_SIZE 16
#pragma pack(1)
///
/// Format Entrypoint Descriptor Entry
///
typedef struct {
UINT8 Type; // Type == 0
UINT8 Type; ///< Type here should be 0
UINT8 Reserved[7];
UINT64 PalProcEntry;
UINT64 SalProcEntry;
@ -258,20 +430,28 @@ typedef struct {
} SAL_ST_ENTRY_POINT_DESCRIPTOR;
#pragma pack(1)
///
/// Format Platform Features Descriptor Entry
///
typedef struct {
UINT8 Type; // Type == 2
UINT8 Type; ///< Type here should be 2
UINT8 PlatformFeatures;
UINT8 Reserved[14];
} SAL_ST_PLATFORM_FEATURES;
#pragma pack()
//
// Value of Platform Feature List
//
#define SAL_PLAT_FEAT_BUS_LOCK 0x01
#define SAL_PLAT_FEAT_PLAT_IPI_HINT 0x02
#define SAL_PLAT_FEAT_PROC_IPI_HINT 0x04
#pragma pack(1)
///
/// Format of Translation Register Descriptor Entry
///
typedef struct {
UINT8 Type; // Type == 3
UINT8 Type; ///< Type here should be 3
UINT8 TRType;
UINT8 TRNumber;
UINT8 Reserved[5];
@ -280,11 +460,16 @@ typedef struct {
UINT64 Reserved1;
} SAL_ST_TR_DECRIPTOR;
#pragma pack()
//
// Type of Translation Register
//
#define EFI_SAL_ST_TR_USAGE_INSTRUCTION 00
#define EFI_SAL_ST_TR_USAGE_DATA 01
#pragma pack(1)
///
/// Definition of Coherence Domain Information
///
typedef struct {
UINT64 NumberOfProcessors;
UINT64 LocalIDRegister;
@ -292,8 +477,11 @@ typedef struct {
#pragma pack()
#pragma pack(1)
///
/// Format of Purge Translation Cache Coherence Domain Entry
///
typedef struct {
UINT8 Type; // Type == 4
UINT8 Type; ///< Type here should be 4
UINT8 Reserved[3];
UINT32 NumberOfDomains;
SAL_COHERENCE_DOMAIN_INFO *DomainInformation;
@ -301,20 +489,20 @@ typedef struct {
#pragma pack()
#pragma pack(1)
///
/// Format of Application Processor Wake-Up Descriptor Entry
///
typedef struct {
UINT8 Type; // Type == 5
UINT8 Type; ///< Type here should be 5
UINT8 WakeUpType;
UINT8 Reserved[6];
UINT64 ExternalInterruptVector;
} SAL_ST_AP_WAKEUP_DECRIPTOR;
#pragma pack()
//
// FIT Entry
//
#define EFI_SAL_FIT_ENTRY_PTR (0x100000000 - 32) // 4GB - 24
#define EFI_SAL_FIT_PALA_ENTRY (0x100000000 - 48) // 4GB - 32
#define EFI_SAL_FIT_PALB_TYPE 01
///
/// Format of Firmware Interface Table (FIT) Entry
///
typedef struct {
UINT64 Address;
UINT8 Size[3];
@ -324,15 +512,37 @@ typedef struct {
UINT8 CheckSumValid : 1;
UINT8 CheckSum;
} EFI_SAL_FIT_ENTRY;
//
// FIT Types
//
#define EFI_SAL_FIT_FIT_HEADER_TYPE 0x00
#define EFI_SAL_FIT_PAL_B_TYPE 0x01
//
// Type from 0x02 to 0x0D is reserved.
//
#define EFI_SAL_FIT_PROCESSOR_SPECIFIC_PAL_A_TYPE 0x0E
#define EFI_SAL_FIT_PAL_A_TYPE 0x0F
//
// OEM-defined type range is from 0x10 to 0x7E.
// Here we defined the PEI_CORE type as 0x10
//
#define EFI_SAL_FIT_PEI_CORE_TYPE 0x10
#define EFI_SAL_FIT_UNUSED_TYPE 0x7F
//
// SAL Common Record Header
// FIT Entry
//
typedef struct {
UINT16 Length;
UINT8 Data[1024];
} SAL_OEM_DATA;
#define EFI_SAL_FIT_ENTRY_PTR (0x100000000 - 32) // 4GB - 24
#define EFI_SAL_FIT_PALA_ENTRY (0x100000000 - 48) // 4GB - 32
#define EFI_SAL_FIT_PALB_TYPE 01
//
// Following definitions are for Error Record Structure
//
///
/// Format of TimeStamp field in Record Header
///
typedef struct {
UINT8 Seconds;
UINT8 Minutes;
@ -343,7 +553,9 @@ typedef struct {
UINT8 Year;
UINT8 Century;
} SAL_TIME_STAMP;
///
/// Definition of Record Header
///
typedef struct {
UINT64 RecordId;
UINT16 Revision;
@ -353,29 +565,35 @@ typedef struct {
SAL_TIME_STAMP TimeStamp;
UINT8 OemPlatformId[16];
} SAL_RECORD_HEADER;
///
/// Definition of Section Header
///
typedef struct {
GUID Guid;
GUID Guid;
UINT16 Revision;
UINT8 ErrorRecoveryInfo;
UINT8 Reserved;
UINT32 SectionLength;
} SAL_SEC_HEADER;
//
// SAL Processor Record
//
///
/// GUID of Processor Machine Check Errors
///
#define SAL_PROCESSOR_ERROR_RECORD_INFO \
{ \
0xe429faf1, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
}
//
// Bit masks for valid bits of MOD_ERROR_INFO
//
#define CHECK_INFO_VALID_BIT_MASK 0x1
#define REQUESTOR_ID_VALID_BIT_MASK 0x2
#define RESPONDER_ID_VALID_BIT_MASK 0x4
#define TARGER_ID_VALID_BIT_MASK 0x8
#define PRECISE_IP_VALID_BIT_MASK 0x10
///
/// Definition of MOD_ERROR_INFO_STRUCT
///
typedef struct {
UINT64 InfoValid : 1;
UINT64 ReqValid : 1;
@ -389,7 +607,9 @@ typedef struct {
UINT64 Target;
UINT64 Ip;
} MOD_ERROR_INFO;
///
/// Definition of CPUID_INFO_STRUCT
///
typedef struct {
UINT8 CpuidInfo[40];
UINT8 Reserved;
@ -399,14 +619,18 @@ typedef struct {
UINT64 FrLow;
UINT64 FrHigh;
} FR_STRUCT;
//
// Bit masks for PSI_STATIC_STRUCT.ValidFieldBits
//
#define MIN_STATE_VALID_BIT_MASK 0x1
#define BR_VALID_BIT_MASK 0x2
#define CR_VALID_BIT_MASK 0x4
#define AR_VALID_BIT_MASK 0x8
#define RR_VALID_BIT_MASK 0x10
#define FR_VALID_BIT_MASK 0x20
///
/// Definition of PSI_STATIC_STRUCT
///
typedef struct {
UINT64 ValidFieldBits;
UINT8 MinStateInfo[1024];
@ -416,13 +640,17 @@ typedef struct {
UINT64 Rr[8];
FR_STRUCT Fr[128];
} PSI_STATIC_STRUCT;
//
// Bit masks for SAL_PROCESSOR_ERROR_RECORD.ValidationBits
//
#define PROC_ERROR_MAP_VALID_BIT_MASK 0x1
#define PROC_STATE_PARAMETER_VALID_BIT_MASK 0x2
#define PROC_CR_LID_VALID_BIT_MASK 0x4
#define PROC_STATIC_STRUCT_VALID_BIT_MASK 0x8
#define CPU_INFO_VALID_BIT_MASK 0x1000000
///
/// Definition of Processor Machine Check Error Record
///
typedef struct {
SAL_SEC_HEADER SectionHeader;
UINT64 ValidationBits;
@ -438,14 +666,16 @@ typedef struct {
PSI_STATIC_STRUCT PsiValidData;
} SAL_PROCESSOR_ERROR_RECORD;
//
// Sal Platform memory Error Record
//
///
/// GUID of Platform Memory Device Error Info
///
#define SAL_MEMORY_ERROR_RECORD_INFO \
{ \
0xe429faf2, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
}
//
// Bit masks for SAL_MEMORY_ERROR_RECORD.ValidationBits
//
#define MEMORY_ERROR_STATUS_VALID_BIT_MASK 0x1
#define MEMORY_PHYSICAL_ADDRESS_VALID_BIT_MASK 0x2
#define MEMORY_ADDR_BIT_MASK 0x4
@ -463,7 +693,9 @@ typedef struct {
#define MEMORY_PLATFORM_BUS_SPECIFIC_DATA_VALID_BIT_MASK 0x4000
#define MEMORY_PLATFORM_OEM_ID_VALID_BIT_MASK 0x8000
#define MEMORY_PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x10000
///
/// Definition of Platform Memory Device Error Info Record
///
typedef struct {
SAL_SEC_HEADER SectionHeader;
UINT64 ValidationBits;
@ -485,14 +717,16 @@ typedef struct {
UINT8 MemPlatformOemId[16];
} SAL_MEMORY_ERROR_RECORD;
//
// PCI BUS Errors
//
///
/// GUID of Platform PCI Bus Error Info
///
#define SAL_PCI_BUS_ERROR_RECORD_INFO \
{ \
0xe429faf4, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
}
//
// Bit masks for SAL_PCI_BUS_ERROR_RECORD.ValidationBits
//
#define PCI_BUS_ERROR_STATUS_VALID_BIT_MASK 0x1
#define PCI_BUS_ERROR_TYPE_VALID_BIT_MASK 0x2
#define PCI_BUS_ID_VALID_BIT_MASK 0x4
@ -509,7 +743,9 @@ typedef struct {
UINT8 BusNumber;
UINT8 SegmentNumber;
} PCI_BUS_ID;
///
/// Definition of Platform PCI Bus Error Info Record
///
typedef struct {
SAL_SEC_HEADER SectionHeader;
UINT64 ValidationBits;
@ -526,21 +762,25 @@ typedef struct {
UINT8 PciBusOemId[16];
} SAL_PCI_BUS_ERROR_RECORD;
//
// PCI Component Errors
//
///
/// GUID of Platform PCI Component Error Info
///
#define SAL_PCI_COMP_ERROR_RECORD_INFO \
{ \
0xe429faf6, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
}
//
// Bit masks for SAL_PCI_COMPONENT_ERROR_RECORD.ValidationBits
//
#define PCI_COMP_ERROR_STATUS_VALID_BIT_MASK 0x1
#define PCI_COMP_INFO_VALID_BIT_MASK 0x2
#define PCI_COMP_MEM_NUM_VALID_BIT_MASK 0x4
#define PCI_COMP_IO_NUM_VALID_BIT_MASK 0x8
#define PCI_COMP_REG_DATA_PAIR_VALID_BIT_MASK 0x10
#define PCI_COMP_OEM_DATA_STRUCT_VALID_BIT_MASK 0x20
///
/// Format of PCI Component Information to identify the device
///
typedef struct {
UINT16 VendorId;
UINT16 DeviceId;
@ -551,7 +791,9 @@ typedef struct {
UINT8 SegmentNumber;
UINT8 Reserved[5];
} PCI_COMP_INFO;
///
/// Definition of Platform PCI Component Error Info
///
typedef struct {
SAL_SEC_HEADER SectionHeader;
UINT64 ValidationBits;
@ -562,14 +804,16 @@ typedef struct {
UINT8 PciBusOemId[16];
} SAL_PCI_COMPONENT_ERROR_RECORD;
//
// Sal Device Errors Info.
//
#define SAL_DEVICE_ERROR_RECORD_INFO \
///
/// Platform SEL Device Error Info
///
#define SAL_SEL_DEVICE_ERROR_RECORD_INFO \
{ \
0xe429faf3, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
}
//
// Bit masks for SAL_SEL_DEVICE_ERROR_RECORD.ValidationBits
//
#define SEL_RECORD_ID_VALID_BIT_MASK 0x1;
#define SEL_RECORD_TYPE_VALID_BIT_MASK 0x2;
#define SEL_GENERATOR_ID_VALID_BIT_MASK 0x4;
@ -580,7 +824,9 @@ typedef struct {
#define SEL_EVENT_DATA1_VALID_BIT_MASK 0x80;
#define SEL_EVENT_DATA2_VALID_BIT_MASK 0x100;
#define SEL_EVENT_DATA3_VALID_BIT_MASK 0x200;
///
/// Definition of Platform SEL Device Error Info Record
///
typedef struct {
SAL_SEC_HEADER SectionHeader;
UINT64 ValidationBits;
@ -595,21 +841,25 @@ typedef struct {
UINT8 Data1;
UINT8 Data2;
UINT8 Data3;
} SAL_DEVICE_ERROR_RECORD;
} SAL_SEL_DEVICE_ERROR_RECORD;
//
// Sal SMBIOS Device Errors Info.
//
///
/// GUID of Platform SMBIOS Device Error Info
///
#define SAL_SMBIOS_ERROR_RECORD_INFO \
{ \
0xe429faf5, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
}
//
// Bit masks for SAL_SMBIOS_DEVICE_ERROR_RECORD.ValidationBits
//
#define SMBIOS_EVENT_TYPE_VALID_BIT_MASK 0x1
#define SMBIOS_LENGTH_VALID_BIT_MASK 0x2
#define SMBIOS_TIME_STAMP_VALID_BIT_MASK 0x4
#define SMBIOS_DATA_VALID_BIT_MASK 0x8
///
/// Definition of Platform SMBIOS Device Error Info Record
///
typedef struct {
SAL_SEC_HEADER SectionHeader;
UINT64 ValidationBits;
@ -619,13 +869,15 @@ typedef struct {
} SAL_SMBIOS_DEVICE_ERROR_RECORD;
///
/// Sal Platform Specific Errors Info.
/// GUID of Platform Specific Error Info
///
#define SAL_PLATFORM_ERROR_RECORD_INFO \
{ \
0xe429faf7, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
}
//
// Bit masks for SAL_PLATFORM_SPECIFIC_ERROR_RECORD.ValidationBits
//
#define PLATFORM_ERROR_STATUS_VALID_BIT_MASK 0x1
#define PLATFORM_REQUESTOR_ID_VALID_BIT_MASK 0x2
#define PLATFORM_RESPONDER_ID_VALID_BIT_MASK 0x4
@ -634,7 +886,9 @@ typedef struct {
#define PLATFORM_OEM_ID_VALID_BIT_MASK 0x20
#define PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x40
#define PLATFORM_OEM_DEVICE_PATH_VALID_BIT_MASK 0x80
///
/// Definition of Platform Specific Error Info Record
///
typedef struct {
SAL_SEC_HEADER SectionHeader;
UINT64 ValidationBits;
@ -647,14 +901,14 @@ typedef struct {
} SAL_PLATFORM_SPECIFIC_ERROR_RECORD;
///
/// Union of all the possible Sal Record Types
/// Union of all the possible SAL Error Record Types
///
typedef union {
SAL_RECORD_HEADER *RecordHeader;
SAL_PROCESSOR_ERROR_RECORD *SalProcessorRecord;
SAL_PCI_BUS_ERROR_RECORD *SalPciBusRecord;
SAL_PCI_COMPONENT_ERROR_RECORD *SalPciComponentRecord;
SAL_DEVICE_ERROR_RECORD *ImpiRecord;
SAL_SEL_DEVICE_ERROR_RECORD *ImpiRecord;
SAL_SMBIOS_DEVICE_ERROR_RECORD *SmbiosRecord;
SAL_PLATFORM_SPECIFIC_ERROR_RECORD *PlatformRecord;
SAL_MEMORY_ERROR_RECORD *MemoryRecord;

94
MdePkg/Include/IndustryStandard/Scsi.h
View File

@ -1,7 +1,7 @@
/** @file
support for SCSI-2 standard
Support for SCSI-2 standard
Copyright (c) 2006, Intel Corporation
Copyright (c) 2006 - 2008, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -33,15 +33,15 @@
#define EFI_SCSI_OP_MODE_SEN6 0x1a
#define EFI_SCSI_OP_MODE_SEN10 0x5a
#define EFI_SCSI_OP_READ_BUFFER 0x3c
#define EFI_SCSI_OP_RECEIVE_DIAG 0x1c
#define EFI_SCSI_OP_REQUEST_SENSE 0x03
#define EFI_SCSI_OP_SEND_DIAG 0x1d
#define EFI_SCSI_OP_TEST_UNIT_READY 0x00
#define EFI_SCSI_OP_WRITE_BUFF 0x3b
//
// Commands unique to Direct Access Devices
// Additional commands for Direct Access Devices
//
#define EFI_SCSI_OP_COMPARE 0x39
#define EFI_SCSI_OP_FORMAT 0x04
#define EFI_SCSI_OP_LOCK_UN_CACHE 0x36
#define EFI_SCSI_OP_PREFETCH 0x34
@ -52,7 +52,6 @@
#define EFI_SCSI_OP_READ_DEFECT 0x37
#define EFI_SCSI_OP_READ_LONG 0x3e
#define EFI_SCSI_OP_REASSIGN_BLK 0x07
#define EFI_SCSI_OP_RECEIVE_DIAG 0x1c
#define EFI_SCSI_OP_RELEASE 0x17
#define EFI_SCSI_OP_REZERO 0x01
#define EFI_SCSI_OP_SEARCH_DATA_E 0x31
@ -72,7 +71,7 @@
#define EFI_SCSI_OP_WRITE_SAME 0x41
//
// Commands unique to Sequential Access Devices
// Additional commands for Sequential Access Devices
//
#define EFI_SCSI_OP_ERASE 0x19
#define EFI_SCSI_OP_LOAD_UNLOAD 0x1b
@ -88,7 +87,7 @@
#define EFI_SCSI_OP_WRITE_FILEMARK 0x10
//
// Commands unique to Printer Devices
// Additional commands for Printer Devices
//
#define EFI_SCSI_OP_PRINT 0x0a
#define EFI_SCSI_OP_SLEW_PRINT 0x0b
@ -96,13 +95,13 @@
#define EFI_SCSI_OP_SYNC_BUFF 0x10
//
// Commands unique to Processor Devices
// Additional commands for Processor Devices
//
#define EFI_SCSI_OP_RECEIVE 0x08
#define EFI_SCSI_OP_SEND 0x0a
//
// Commands unique to Write-Once Devices
// Additional commands for Write-Once Devices
//
#define EFI_SCSI_OP_MEDIUM_SCAN 0x38
#define EFI_SCSI_OP_SEARCH_DAT_E10 0x31
@ -120,7 +119,7 @@
#define EFI_SCSI_OP_WRITE_VERIFY12 0xae
//
// Commands unique to CD-ROM Devices
// Additional commands for CD-ROM Devices
//
#define EFI_SCSI_OP_PLAY_AUD_10 0x45
#define EFI_SCSI_OP_PLAY_AUD_12 0xa5
@ -134,7 +133,7 @@
#define EFI_SCSI_OP_READ_TOC 0x43
//
// Commands unique to Scanner Devices
// Additional commands for Scanner Devices
//
#define EFI_SCSI_OP_GET_DATABUFF_STAT 0x34
#define EFI_SCSI_OP_GET_WINDOW 0x25
@ -143,12 +142,12 @@
#define EFI_SCSI_OP_SET_WINDOW 0x24
//
// Commands unique to Optical Memory Devices
// Additional commands for Optical Memory Devices
//
#define EFI_SCSI_OP_UPDATE_BLOCK 0x3d
//
// Commands unique to Medium Changer Devices
// Additional commands for Medium Changer Devices
//
#define EFI_SCSI_OP_EXCHANGE_MEDIUM 0xa6
#define EFI_SCSI_OP_INIT_ELEMENT_STAT 0x07
@ -157,7 +156,7 @@
#define EFI_SCSI_OP_SEND_VOL_TAG 0xb6
//
// Commands unique to Communition Devices
// Additional commands for Communition Devices
//
#define EFI_SCSI_OP_GET_MESSAGE6 0x08
#define EFI_SCSI_OP_GET_MESSAGE10 0x28
@ -175,23 +174,27 @@
//
// Peripheral Device Type Definitions
//
#define EFI_SCSI_TYPE_DISK 0x00 // Disk device
#define EFI_SCSI_TYPE_TAPE 0x01 // Tape device
#define EFI_SCSI_TYPE_PRINTER 0x02 // Printer
#define EFI_SCSI_TYPE_PROCESSOR 0x03 // Processor
#define EFI_SCSI_TYPE_WORM 0x04 // Write-once read-multiple
#define EFI_SCSI_TYPE_CDROM 0x05 // CD-ROM device
#define EFI_SCSI_TYPE_SCANNER 0x06 // Scanner device
#define EFI_SCSI_TYPE_OPTICAL 0x07 // Optical memory device
#define EFI_SCSI_TYPE_MEDIUMCHANGER 0x08 // Medium Changer device
#define EFI_SCSI_TYPE_COMMUNICATION 0x09 // Communications device
#define EFI_SCSI_TYPE_RESERVED_LOW 0x0A // Reserved (low)
#define EFI_SCSI_TYPE_RESERVED_HIGH 0x1E // Reserved (high)
#define EFI_SCSI_TYPE_UNKNOWN 0x1F // Unknown or no device type
#define EFI_SCSI_TYPE_DISK 0x00 ///< Direct-access device (e.g. magnetic disk)
#define EFI_SCSI_TYPE_TAPE 0x01 ///< Sequential-access device (e.g. magnetic tape)
#define EFI_SCSI_TYPE_PRINTER 0x02 ///< Printer device
#define EFI_SCSI_TYPE_PROCESSOR 0x03 ///< Processor device
#define EFI_SCSI_TYPE_WORM 0x04 ///< Write-once device (e.g. some optical disks)
#define EFI_SCSI_TYPE_CDROM 0x05 ///< CD-ROM device
#define EFI_SCSI_TYPE_SCANNER 0x06 ///< Scanner device
#define EFI_SCSI_TYPE_OPTICAL 0x07 ///< Optical memory device (e.g. some optical disks)
#define EFI_SCSI_TYPE_MEDIUMCHANGER 0x08 ///< Medium changer device (e.g. jukeboxes)
#define EFI_SCSI_TYPE_COMMUNICATION 0x09 ///< Communications device
#define EFI_SCSI_TYPE_ASCIT8_1 0x0A ///< Defined by ASC IT8 (Graphic arts pre-press devices)
#define EFI_SCSI_TYPE_ASCIT8_2 0x0B ///< Defined by ASC IT8 (Graphic arts pre-press devices)
//
// 0Ch - 1Eh are reserved
//
#define EFI_SCSI_TYPE_UNKNOWN 0x1F ///< Unknown or no device type
#pragma pack(1)
//
// Data structures for scsi command use
//
///
/// Standard INQUIRY data format
///
typedef struct {
UINT8 Peripheral_Type : 5;
UINT8 Peripheral_Qualifier : 3;
@ -203,6 +206,9 @@ typedef struct {
UINT8 Reserved_5_95[95 - 5 + 1];
} EFI_SCSI_INQUIRY_DATA;
///
/// Error codes 70h and 71h sense data format
///
typedef struct {
UINT8 Error_Code : 7;
UINT8 Valid : 1;
@ -212,11 +218,11 @@ typedef struct {
UINT8 ILI : 1;
UINT8 Reserved_22 : 2;
UINT8 Information_3_6[4];
UINT8 Addnl_Sense_Length; // n - 7
UINT8 Addnl_Sense_Length; ///< Additional sense length (n-7)
UINT8 Vendor_Specific_8_11[4];
UINT8 Addnl_Sense_Code; // mandatory
UINT8 Addnl_Sense_Code_Qualifier; // mandatory
UINT8 Field_Replaceable_Unit_Code; // optional
UINT8 Addnl_Sense_Code; ///< Additional sense code
UINT8 Addnl_Sense_Code_Qualifier; ///< Additional sense code qualifier
UINT8 Field_Replaceable_Unit_Code; ///< Field replaceable unit code
UINT8 Reserved_15_17[3];
} EFI_SCSI_SENSE_DATA;
@ -232,10 +238,10 @@ typedef struct {
} EFI_SCSI_DISK_CAPACITY_DATA;
#pragma pack()
//
// Sense Key
//
#define EFI_SCSI_REQUEST_SENSE_ERROR (0x70)
#define EFI_SCSI_SK_NO_SENSE (0x0)
#define EFI_SCSI_SK_RECOVERY_ERROR (0x1)
#define EFI_SCSI_SK_NOT_READY (0x2)
@ -254,9 +260,13 @@ typedef struct {
#define EFI_SCSI_SK_RESERVED_F (0xF)
//
// Additional Sense Codes
// Additional Sense Codes and Sense Code Qualifiers.
// Only some frequently used additional sense codes and qualifiers are
// defined here. Please refer to SCSI standard for full value definition.
//
#define EFI_SCSI_ASC_NOT_READY (0x04)
#define EFI_SCSI_ASCQ_IN_PROGRESS (0x01)
#define EFI_SCSI_ASC_MEDIA_ERR1 (0x10)
#define EFI_SCSI_ASC_MEDIA_ERR2 (0x11)
#define EFI_SCSI_ASC_MEDIA_ERR3 (0x14)
@ -267,19 +277,9 @@ typedef struct {
#define EFI_SCSI_ASC_INVALID_FIELD (0x24)
#define EFI_SCSI_ASC_WRITE_PROTECTED (0x27)
#define EFI_SCSI_ASC_MEDIA_CHANGE (0x28)
#define EFI_SCSI_ASC_RESET (0x29) /* Power On Reset or Bus Reset occurred */
#define EFI_SCSI_ASC_RESET (0x29) ///<Power On Reset or Bus Reset occurred
#define EFI_SCSI_ASC_ILLEGAL_FIELD (0x26)
#define EFI_SCSI_ASC_NO_MEDIA (0x3A)
#define EFI_SCSI_ASC_ILLEGAL_MODE_FOR_THIS_TRACK (0x64)
///
/// Additional Sense Code Qualifier
///
#define EFI_SCSI_ASCQ_IN_PROGRESS (0x01)
///
/// Max bytes needed to represent ID of a SCSI device
///
#define EFI_SCSI_TARGET_MAX_BYTES (0x10)
#endif

26
MdePkg/Include/IndustryStandard/SdramSpd.h
View File

@ -1,7 +1,7 @@
/** @file
This file contains definitions for the SPD fields on an SDRAM.
Copyright (c) 2007, Intel Corporation
Copyright (c) 2007 - 2008, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -32,12 +32,12 @@
#define SPD_SDRAM_CAS_LATENCY 18
#define SPD_SDRAM_MODULE_ATTR 21
#define SPD_SDRAM_TCLK1_PULSE 9 // cycle time for highest cas latency
#define SPD_SDRAM_TAC1_PULSE 10 // access time for highest cas latency
#define SPD_SDRAM_TCLK2_PULSE 23 // cycle time for 2nd highest cas latency
#define SPD_SDRAM_TAC2_PULSE 24 // access time for 2nd highest cas latency
#define SPD_SDRAM_TCLK3_PULSE 25 // cycle time for 3rd highest cas latency
#define SPD_SDRAM_TAC3_PULSE 26 // access time for 3rd highest cas latency
#define SPD_SDRAM_TCLK1_PULSE 9 ///< cycle time for highest cas latency
#define SPD_SDRAM_TAC1_PULSE 10 ///< access time for highest cas latency
#define SPD_SDRAM_TCLK2_PULSE 23 ///< cycle time for 2nd highest cas latency
#define SPD_SDRAM_TAC2_PULSE 24 ///< access time for 2nd highest cas latency
#define SPD_SDRAM_TCLK3_PULSE 25 ///< cycle time for 3rd highest cas latency
#define SPD_SDRAM_TAC3_PULSE 26 ///< access time for 3rd highest cas latency
#define SPD_SDRAM_MIN_PRECHARGE 27
#define SPD_SDRAM_ACTIVE_MIN 28
#define SPD_SDRAM_RAS_CAS 29
@ -47,15 +47,15 @@
//
// Memory Type Definitions
//
#define SPD_VAL_SDR_TYPE 4 // SDR SDRAM memory
#define SPD_VAL_DDR_TYPE 7 // DDR SDRAM memory
#define SPD_VAL_DDR2_TYPE 8 // DDR2 SDRAM memory
#define SPD_VAL_SDR_TYPE 4 ///< SDR SDRAM memory
#define SPD_VAL_DDR_TYPE 7 ///< DDR SDRAM memory
#define SPD_VAL_DDR2_TYPE 8 ///< DDR2 SDRAM memory
//
// ECC Type Definitions
//
#define SPD_ECC_TYPE_NONE 0x00 // No error checking
#define SPD_ECC_TYPE_PARITY 0x01 // No error checking
#define SPD_ECC_TYPE_ECC 0x02 // Error checking only
#define SPD_ECC_TYPE_NONE 0x00 ///< No error checking
#define SPD_ECC_TYPE_PARITY 0x01 ///< No error checking
#define SPD_ECC_TYPE_ECC 0x02 ///< Error checking only
//
// Module Attributes (Bit positions)
//

31
MdePkg/Include/IndustryStandard/SerialPortConsoleRedirectionTable.h
View File

@ -2,7 +2,7 @@
ACPI Serial Port Console Redirection Table as defined by Microsoft in
http://www.microsoft.com/whdc/system/platform/server/spcr.mspx
Copyright (c) 2007, Intel Corporation
Copyright (c) 2007 - 2008, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -29,7 +29,7 @@
#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION 0x01
///
/// SPCR Structure Definition
/// Serial Port Console Redirection Table Format
///
typedef struct {
EFI_ACPI_DESCRIPTION_HEADER Header;
@ -64,14 +64,31 @@ typedef struct {
//
// Interface Type
//
///
/// Full 16550 interface
///
#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_16550 0
///
/// Full 16450 interface
///
#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_16450 1
//
// Interrupt Type
//
///
/// PC-AT-compatible dual-8259 IRQ interrupt
///
#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_8259 0x1
///
/// I/O APIC interrupt (Global System Interrupt)
///
#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_APIC 0x2
///
/// I/O SAPIC interrupt (Global System Interrupt)
///
#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_SAPIC 0x4
//
@ -95,8 +112,18 @@ typedef struct {
//
// Flow Control
//
///
/// DCD required for transmit
///
#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_FLOW_CONTROL_DCD 0x1
///
/// RTS/CTS hardware flow control
///
#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_FLOW_CONTROL_RTS_CTS 0x2
///
/// XON/XOFF software control
///
#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_FLOW_CONTROL_XON_XOFF 0x4
//

152
MdePkg/Include/IndustryStandard/SmBios.h
View File

@ -1,8 +1,7 @@
/** @file
Industry Standard Definitions of SMBIOS tables.
Industry Standard Definitions of SMBIOS Table Specification v2.6
Copyright (c) 2006 - 2007, Intel Corporation All rights
Copyright (c) 2006 - 2008, Intel Corporation All rights
reserved. This program and the accompanying materials are
licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -11,15 +10,13 @@
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Revision Reference: SMBIOS 2.0
**/
#ifndef __SMBIOS_STANDARD_H__
#define __SMBIOS_STANDARD_H__
//
// Smbios Table Entry Point Structure
//
///
/// Smbios Table Entry Point Structure
///
#pragma pack(1)
typedef struct {
UINT8 AnchorString[4];
@ -49,6 +46,9 @@ typedef struct {
typedef UINT8 SMBIOS_TABLE_STRING;
///
/// BIOS Information (Type 0)
///
typedef struct {
SMBIOS_STRUCTURE Hdr;
SMBIOS_TABLE_STRING Vendor;
@ -64,6 +64,9 @@ typedef struct {
UINT8 EmbeddedControllerFirmwareMinorRelease;
} SMBIOS_TABLE_TYPE0;
///
/// System Information (Type 1)
///
typedef struct {
SMBIOS_STRUCTURE Hdr;
SMBIOS_TABLE_STRING Manufacturer;
@ -76,6 +79,9 @@ typedef struct {
SMBIOS_TABLE_STRING Family;
} SMBIOS_TABLE_TYPE1;
///
/// Base Board (or Module) Information (Type 2)
///
typedef struct {
SMBIOS_STRUCTURE Hdr;
SMBIOS_TABLE_STRING Manufacturer;
@ -97,6 +103,9 @@ typedef struct {
UINT8 ContainedElementMaximum;
} CONTAINED_ELEMENT;
///
/// System Enclosure or Chassis (Type 3)
///
typedef struct {
SMBIOS_STRUCTURE Hdr;
SMBIOS_TABLE_STRING Manufacturer;
@ -116,6 +125,9 @@ typedef struct {
CONTAINED_ELEMENT ContainedElements[1];
} SMBIOS_TABLE_TYPE3;
///
/// Processor Information (Type 4)
///
typedef struct {
SMBIOS_STRUCTURE Hdr;
UINT8 Socket;
@ -149,6 +161,9 @@ typedef struct {
UINT16 ProcessorFamily2;
} SMBIOS_TABLE_TYPE4;
///
/// Memory Controller Information (Type 5, Obsolete)
///
typedef struct {
SMBIOS_STRUCTURE Hdr;
UINT8 ErrDetectMethod;
@ -161,9 +176,11 @@ typedef struct {
UINT8 MemoryModuleVoltage;
UINT8 AssociatedMemorySlotNum;
UINT16 MemoryModuleConfigHandles[1];
// UINT8 EnableErrCorrectCapabilities;
} SMBIOS_TABLE_TYPE5;
///
/// Memory Module Information (Type 6, Obsolete)
///
typedef struct {
SMBIOS_STRUCTURE Hdr;
SMBIOS_TABLE_STRING SocketDesignation;
@ -175,6 +192,9 @@ typedef struct {
UINT8 ErrorStatus;
} SMBIOS_TABLE_TYPE6;
///
/// Cache Information (Type 7)
///
typedef struct {
SMBIOS_STRUCTURE Hdr;
SMBIOS_TABLE_STRING SocketDesignation;
@ -189,6 +209,9 @@ typedef struct {
UINT8 Associativity;
} SMBIOS_TABLE_TYPE7;
///
/// Port Connector Information (Type 8)
///
typedef struct {
SMBIOS_STRUCTURE Hdr;
SMBIOS_TABLE_STRING InternalReferenceDesignator;
@ -198,6 +221,9 @@ typedef struct {
UINT8 PortType;
} SMBIOS_TABLE_TYPE8;
///
/// System Slots (Type 9)
///
typedef struct {
SMBIOS_STRUCTURE Hdr;
SMBIOS_TABLE_STRING SlotDesignation;
@ -221,21 +247,33 @@ typedef struct {
SMBIOS_TABLE_STRING DescriptionString;
} DEVICE_STRUCT;
///
/// On Board Devices Information (Type 10, obsolete)
///
typedef struct {
SMBIOS_STRUCTURE Hdr;
DEVICE_STRUCT Device[1];
} SMBIOS_TABLE_TYPE10;
///
/// OEM Strings (Type 11)
///
typedef struct {
SMBIOS_STRUCTURE Hdr;
UINT8 StringCount;
} SMBIOS_TABLE_TYPE11;
///
/// System Configuration Options (Type 12)
///
typedef struct {
SMBIOS_STRUCTURE Hdr;
UINT8 StringCount;
} SMBIOS_TABLE_TYPE12;
///
/// BIOS Language Information (Type 13)
///
typedef struct {
SMBIOS_STRUCTURE Hdr;
UINT8 InstallableLanguages;
@ -249,6 +287,9 @@ typedef struct {
UINT16 ItemHandle;
} GROUP_STRUCT;
///
/// Group Associations (Type 14)
///
typedef struct {
SMBIOS_STRUCTURE Hdr;
SMBIOS_TABLE_STRING GroupName;
@ -260,6 +301,9 @@ typedef struct {
UINT8 DataFormatType;
} EVENT_LOG_TYPE;
///
/// System Event Log (Type 15)
///
typedef struct {
SMBIOS_STRUCTURE Hdr;
UINT16 LogAreaLength;
@ -275,6 +319,9 @@ typedef struct {
EVENT_LOG_TYPE EventLogTypeDescriptors[1];
} SMBIOS_TABLE_TYPE15;
///
/// Physical Memory Array (Type 16)
///
typedef struct {
SMBIOS_STRUCTURE Hdr;
UINT8 Location;
@ -285,6 +332,9 @@ typedef struct {
UINT16 NumberOfMemoryDevices;
} SMBIOS_TABLE_TYPE16;
///
/// Memory Device (Type 17)
///
typedef struct {
SMBIOS_STRUCTURE Hdr;
UINT16 MemoryArrayHandle;
@ -309,6 +359,9 @@ typedef struct {
UINT8 Attributes;
} SMBIOS_TABLE_TYPE17;
///
/// 32-bit Memory Error Information (Type 18)
///
typedef struct {
SMBIOS_STRUCTURE Hdr;
UINT8 ErrorType;
@ -320,6 +373,9 @@ typedef struct {
UINT32 ErrorResolution;
} SMBIOS_TABLE_TYPE18;
///
/// Memory Array Mapped Address (Type 19)
///
typedef struct {
SMBIOS_STRUCTURE Hdr;
UINT32 StartingAddress;
@ -328,6 +384,9 @@ typedef struct {
UINT8 PartitionWidth;
} SMBIOS_TABLE_TYPE19;
///
/// Memory Device Mapped Address (Type 20)
///
typedef struct {
SMBIOS_STRUCTURE Hdr;
UINT32 StartingAddress;
@ -339,6 +398,9 @@ typedef struct {
UINT8 InterleavedDataDepth;
} SMBIOS_TABLE_TYPE20;
///
/// Built-in Pointing Device (Type 21)
///
typedef struct {
SMBIOS_STRUCTURE Hdr;
UINT8 Type;
@ -346,6 +408,9 @@ typedef struct {
UINT8 NumberOfButtons;
} SMBIOS_TABLE_TYPE21;
///
/// Portable Battery (Type 22)
///
typedef struct {
SMBIOS_STRUCTURE Hdr;
SMBIOS_TABLE_STRING Location;
@ -365,6 +430,9 @@ typedef struct {
UINT32 OEMSpecific;
} SMBIOS_TABLE_TYPE22;
///
/// System Reset (Type 23)
///
typedef struct {
SMBIOS_STRUCTURE Hdr;
UINT8 Capabilities;
@ -374,11 +442,17 @@ typedef struct {
UINT16 Timeout;
} SMBIOS_TABLE_TYPE23;
///
/// Hardware Security (Type 24)
///
typedef struct {
SMBIOS_STRUCTURE Hdr;
UINT8 HardwareSecuritySettings;
} SMBIOS_TABLE_TYPE24;
///
/// System Power Controls (Type 25)
///
typedef struct {
SMBIOS_STRUCTURE Hdr;
UINT8 NextScheduledPowerOnMonth;
@ -388,6 +462,9 @@ typedef struct {
UINT8 NextScheduledPowerOnSecond;
} SMBIOS_TABLE_TYPE25;
///
/// Voltage Probe (Type 26)
///
typedef struct {
SMBIOS_STRUCTURE Hdr;
SMBIOS_TABLE_STRING Description;
@ -401,6 +478,9 @@ typedef struct {
UINT16 NominalValue;
} SMBIOS_TABLE_TYPE26;
///
/// Cooling Device (Type 27)
///
typedef struct {
SMBIOS_STRUCTURE Hdr;
UINT16 TemperatureProbeHandle;
@ -410,6 +490,9 @@ typedef struct {
UINT16 NominalSpeed;
} SMBIOS_TABLE_TYPE27;
///
/// Temperature Probe (Type 28)
///
typedef struct {
SMBIOS_STRUCTURE Hdr;
SMBIOS_TABLE_STRING Description;
@ -423,6 +506,9 @@ typedef struct {
UINT16 NominalValue;
} SMBIOS_TABLE_TYPE28;
///
/// Electrical Current Probe (Type 29)
///
typedef struct {
SMBIOS_STRUCTURE Hdr;
SMBIOS_TABLE_STRING Description;
@ -436,12 +522,18 @@ typedef struct {
UINT16 NominalValue;
} SMBIOS_TABLE_TYPE29;
///
/// Out-of-Band Remote Access (Type 30)
///
typedef struct {
SMBIOS_STRUCTURE Hdr;
SMBIOS_TABLE_STRING ManufacturerName;
UINT8 Connections;
} SMBIOS_TABLE_TYPE30;
///
/// Boot Integrity Services (BIS) Entry Point (Type 31)
///
typedef struct {
SMBIOS_STRUCTURE Hdr;
UINT8 Checksum;
@ -453,12 +545,18 @@ typedef struct {
UINT32 Reserved4;
} SMBIOS_TABLE_TYPE31;
///
/// System Boot Information (Type 32)
///
typedef struct {
SMBIOS_STRUCTURE Hdr;
UINT8 Reserved[6];
UINT8 BootStatus[1];
} SMBIOS_TABLE_TYPE32;
///
/// 64-bit Memory Error Information (Type 33)
///
typedef struct {
SMBIOS_STRUCTURE Hdr;
UINT8 ErrorType;
@ -470,6 +568,9 @@ typedef struct {
UINT32 ErrorResolution;
} SMBIOS_TABLE_TYPE33;
///
/// Management Device (Type 34)
///
typedef struct {
SMBIOS_STRUCTURE Hdr;
SMBIOS_TABLE_STRING Description;
@ -478,6 +579,9 @@ typedef struct {
UINT8 AddressType;
} SMBIOS_TABLE_TYPE34;
///
/// Management Device Component (Type 35)
///
typedef struct {
SMBIOS_STRUCTURE Hdr;
SMBIOS_TABLE_STRING Description;
@ -486,6 +590,9 @@ typedef struct {
UINT16 ThresholdHandle;
} SMBIOS_TABLE_TYPE35;
///
/// Management Device Threshold Data (Type 36)
///
typedef struct {
SMBIOS_STRUCTURE Hdr;
UINT16 LowerThresholdNonCritical;
@ -501,6 +608,9 @@ typedef struct {
UINT16 DeviceHandle;
} MEMORY_DEVICE;
///
/// Memory Channel (Type 37)
///
typedef struct {
SMBIOS_STRUCTURE Hdr;
UINT8 ChannelType;
@ -509,6 +619,9 @@ typedef struct {
MEMORY_DEVICE MemoryDevice[1];
} SMBIOS_TABLE_TYPE37;
///
/// IPMI Device Information (Type 38)
///
typedef struct {
SMBIOS_STRUCTURE Hdr;
UINT8 InterfaceType;
@ -520,6 +633,9 @@ typedef struct {
UINT8 InterruptNumber;
} SMBIOS_TABLE_TYPE38;
///
/// System Power Supply (Type 39)
///
typedef struct {
SMBIOS_STRUCTURE Hdr;
UINT8 PowerUnitGroup;
@ -537,9 +653,6 @@ typedef struct {
UINT16 InputCurrentProbeHandle;
} SMBIOS_TABLE_TYPE39;
//
// Add type 40 and type 41 for smbios 2.6
//
typedef struct {
UINT8 EntryLength;
UINT16 ReferencedHandle;
@ -548,12 +661,18 @@ typedef struct {
UINT8 Value[1];
}ADDITIONAL_INFORMATION_ENTRY;
///
/// Additional Information (Type 40)
///
typedef struct {
SMBIOS_STRUCTURE Hdr;
UINT8 NumberOfAdditionalInformationEntries;
ADDITIONAL_INFORMATION_ENTRY AdditionalInfoEntries[1];
} SMBIOS_TABLE_TYPE40;
///
/// Onboard Devices Extended Information (Type 41)
///
typedef struct {
SMBIOS_STRUCTURE Hdr;
SMBIOS_TABLE_STRING ReferenceDesignation;
@ -564,14 +683,23 @@ typedef struct {
UINT8 DevFuncNum;
} SMBIOS_TABLE_TYPE41;
///
/// Inactive (Type 126)
///
typedef struct {
SMBIOS_STRUCTURE Hdr;
} SMBIOS_TABLE_TYPE126;
///
/// End-of-Table (Type 127)
///
typedef struct {
SMBIOS_STRUCTURE Hdr;
} SMBIOS_TABLE_TYPE127;
///
/// Union of all the possible SMBIOS record types
///
typedef union {
SMBIOS_STRUCTURE *Hdr;
SMBIOS_TABLE_TYPE0 *Type0;

13
MdePkg/Include/IndustryStandard/SmBus.h
View File

@ -1,8 +1,7 @@
/** @file
This file declares the SMBus definitions defined in SmBus Specifciation
V2.0.
This file declares the SMBus definitions defined in SmBus Specifciation V2.0.
Copyright (c) 2007, Intel Corporation
Copyright (c) 2007 - 2008, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -11,9 +10,6 @@
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
@par Revision Reference:
These definitions are defined in System Management Bus (SmBus) Specification V2.0.
**/
#ifndef _SMBUS_H_
@ -35,12 +31,15 @@ typedef struct {
} EFI_SMBUS_UDID;
///
/// Smbus Device Address, Smbus Device Command, Smbus Operations
/// Smbus Device Address
///
typedef struct {
UINTN SmbusDeviceAddress : 7;
} EFI_SMBUS_DEVICE_ADDRESS;
///
/// Smbus Operations
///
typedef enum _EFI_SMBUS_OPERATION
{
EfiSmbusQuickRead,

1217
MdePkg/Include/IndustryStandard/Tpm12.h
View File

File diff suppressed because it is too large Load Diff

38
MdePkg/Include/IndustryStandard/Usb.h
View File

@ -1,7 +1,7 @@
/** @file
Support for USB 1.1 standard.
Support for USB 2.0 standard.
Copyright (c) 2006 - 2007, Intel Corporation
Copyright (c) 2006 - 2008, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -17,7 +17,7 @@
//
// Standard device request and request type
// By [Spec-USB20/Chapter-9.4]
// USB 2.0 spec, Section 9.4
//
#define USB_DEV_GET_STATUS 0x00
#define USB_DEV_GET_STATUS_REQ_TYPE_D 0x80 // Receiver : Device
@ -63,6 +63,11 @@
// USB standard descriptors and reqeust
//
#pragma pack(1)
///
/// Format of Setup Data for USB Device Requests
/// USB 2.0 spec, Section 9.3
///
typedef struct {
UINT8 RequestType;
UINT8 Request;
@ -71,6 +76,10 @@ typedef struct {
UINT16 Length;
} USB_DEVICE_REQUEST;
///
/// Standard Device Descriptor
/// USB 2.0 spec, Section 9.6.1
///
typedef struct {
UINT8 Length;
UINT8 DescriptorType;
@ -88,6 +97,10 @@ typedef struct {
UINT8 NumConfigurations;
} USB_DEVICE_DESCRIPTOR;
///
/// Standard Configuration Descriptor
/// USB 2.0 spec, Section 9.6.3
///
typedef struct {
UINT8 Length;
UINT8 DescriptorType;
@ -99,6 +112,10 @@ typedef struct {
UINT8 MaxPower;
} USB_CONFIG_DESCRIPTOR;
///
/// Standard Interface Descriptor
/// USB 2.0 spec, Section 9.6.5
///
typedef struct {
UINT8 Length;
UINT8 DescriptorType;
@ -111,6 +128,10 @@ typedef struct {
UINT8 Interface;
} USB_INTERFACE_DESCRIPTOR;
///
/// Standard Endpoint Descriptor
/// USB 2.0 spec, Section 9.6.6
///
typedef struct {
UINT8 Length;
UINT8 DescriptorType;
@ -120,6 +141,10 @@ typedef struct {
UINT8 Interval;
} USB_ENDPOINT_DESCRIPTOR;
///
/// UNICODE String Descriptor
/// USB 2.0 spec, Section 9.6.7
///
typedef struct {
UINT8 Length;
UINT8 DescriptorType;
@ -196,7 +221,8 @@ typedef enum {
//
// HID constants definition, see HID rev1.0
// HID constants definition, see Device Class Definition
// for Human Interface Devices (HID) rev1.11
//
//
@ -314,6 +340,10 @@ typedef struct hid_class_descriptor {
UINT16 DescriptorLength;
} EFI_USB_HID_CLASS_DESCRIPTOR;
///
/// The HID descriptor identifies the length and type
/// of subordinate descriptors for a device.
///
typedef struct hid_descriptor {
UINT8 Length;
UINT8 DescriptorType;

13
MdePkg/Include/IndustryStandard/WatchdogActionTable.h
View File

@ -1,6 +1,6 @@
/** @file
ACPI Watchdog Action Table as defined at
Microsoft Hardware Watchdog Timer Specification.
ACPI Watchdog Action Table (WADT) as defined at
Microsoft Hardware Watchdog Timers Design Specification
Copyright (c) 2008, Intel Corporation
All rights reserved. This program and the accompanying materials
@ -41,6 +41,9 @@ typedef struct {
UINT32 NumberWatchdogInstructionEntries;
} EFI_ACPI_WATCHDOG_ACTION_1_0_TABLE;
///
/// Watchdog Instruction Entries
///
typedef struct {
UINT8 WatchdogAction;
UINT8 InstructionFlags;
@ -57,9 +60,9 @@ typedef struct {
///
#define EFI_ACPI_WATCHDOG_ACTION_1_0_TABLE_REVISION 0x01
///
/// WDAT 1.0 Flags
///
//
// WDAT 1.0 Flags
//
#define EFI_ACPI_WDAT_1_0_WATCHDOG_ENABLED 0x1
#define EFI_ACPI_WDAT_1_0_WATCHDOG_STOPPED_IN_SLEEP_STATE 0x80

65
MdePkg/Include/IndustryStandard/WatchdogResourceTable.h
View File

@ -1,8 +1,8 @@
/** @file
ACPI Watchdog Resource Table as defined at
Microsoft Hardware Watchdog Timer Specification.
ACPI Watchdog Resource Table (WDRT) as defined at
Microsoft Windows Hardware Developer Central.
Copyright (c) 2006 - 2007, Intel Corporation
Copyright (c) 2006 - 2008, Intel Corporation
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@ -39,38 +39,12 @@ typedef struct {
UINT8 Units;
} EFI_ACPI_WATCHDOG_RESOURCE_1_0_TABLE;
typedef struct {
EFI_ACPI_DESCRIPTION_HEADER Header;
UINT32 WatchdogHeaderLength;
UINT8 PCISegment;
UINT8 PCIBusNumber;
UINT8 PCIDeviceNumber;
UINT8 PCIFunctionNumber;
UINT32 TimerPeriod;
UINT32 MaxCount;
UINT32 MinCount;
UINT8 WatchdogFlags;
UINT8 Reserved_57[3];
UINT32 NumberWatchdogInstructionEntries;
} EFI_ACPI_WATCHDOG_RESOURCE_2_0_TABLE;
typedef struct {
UINT8 WatchdogAction;
UINT8 InstructionFlags;
UINT8 Reserved_2;
UINT8 RegisterSize;
EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE RegisterRegion;
UINT32 Value;
UINT32 Mask;
} EFI_ACPI_WATCHDOG_RESOURCE_2_0_WATCHDOG_ACTION_INSTRUCTION_ENTRY;
#pragma pack()
//
// WDRT Revision (defined in spec)
//
#define EFI_ACPI_WATCHDOG_RESOURCE_1_0_TABLE_REVISION 0x01
#define EFI_ACPI_WATCHDOG_RESOURCE_2_0_TABLE_REVISION 0x02
//
// WDRT 1.0 Count Unit
@ -79,37 +53,4 @@ typedef struct {
#define EFI_ACPI_WDRT_1_0_COUNT_UNIT_100_MILLISEC_PER_COUNT 2
#define EFI_ACPI_WDRT_1_0_COUNT_UNIT_10_MILLISEC_PER_COUNT 3
//
// WDRT 2.0 Flags
//
#define EFI_ACPI_WDRT_2_0_WATCHDOG_ENABLED 0x1
#define EFI_ACPI_WDRT_2_0_WATCHDOG_STOPPED_IN_SLEEP_STATE 0x80
//
// WDRT 2.0 Watchdog Actions
//
#define EFI_ACPI_WDRT_2_0_WATCHDOG_ACTION_RESET 0x1
#define EFI_ACPI_WDRT_2_0_WATCHDOG_ACTION_QUERY_CURRENT_COUNTDOWN_PERIOD 0x4
#define EFI_ACPI_WDRT_2_0_WATCHDOG_ACTION_QUERY_COUNTDOWN_PERIOD 0x5
#define EFI_ACPI_WDRT_2_0_WATCHDOG_ACTION_SET_COUNTDOWN_PERIOD 0x6
#define EFI_ACPI_WDRT_2_0_WATCHDOG_ACTION_QUERY_RUNNING_STATE 0x8
#define EFI_ACPI_WDRT_2_0_WATCHDOG_ACTION_SET_RUNNING_STATE 0x9
#define EFI_ACPI_WDRT_2_0_WATCHDOG_ACTION_QUERY_STOPPED_STATE 0xA
#define EFI_ACPI_WDRT_2_0_WATCHDOG_ACTION_SET_STOPPED_STATE 0xB
#define EFI_ACPI_WDRT_2_0_WATCHDOG_ACTION_QUERY_REBOOT 0x10
#define EFI_ACPI_WDRT_2_0_WATCHDOG_ACTION_SET_REBOOT 0x11
#define EFI_ACPI_WDRT_2_0_WATCHDOG_ACTION_QUERY_SHUTDOWN 0x12
#define EFI_ACPI_WDRT_2_0_WATCHDOG_ACTION_SET_SHUTDOWN 0x13
#define EFI_ACPI_WDRT_2_0_WATCHDOG_ACTION_QUERY_WATCHDOG_STATUS 0x20
#define EFI_ACPI_WDRT_2_0_WATCHDOG_ACTION_SET_WATCHDOG_STATUS 0x21
//
// WDRT 2.0 Watchdog Action Entry Instruction Flags
//
#define EFI_ACPI_WDRT_2_0_WATCHDOG_INSTRUCTION_READ_VALUE 0x0
#define EFI_ACPI_WDRT_2_0_WATCHDOG_INSTRUCTION_READ_COUNTDOWN 0x1
#define EFI_ACPI_WDRT_2_0_WATCHDOG_INSTRUCTION_WRITE_VALUE 0x2
#define EFI_ACPI_WDRT_2_0_WATCHDOG_INSTRUCTION_WRITE_COUNTDOWN 0x3
#define EFI_ACPI_WDRT_2_0_WATCHDOG_INSTRUCTION_PRESERVE_REGISTER 0x80
#endif