tyler.durden/audk
1
0
Fork 0
mirror of https://github.com/acidanthera/audk.git synced 2025-07-23 05:34:31 +02:00
Code Issues Packages Projects Releases Wiki Activity

Added DebugAgentTimerLib. Cleaned up .h files and other code.

Browse Source 
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10332 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
andrewfish 2010-04-03 00:34:19 +00:00
parent 1f44ee1077
commit 43263288dd
35 changed files with 558 additions and 308 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Omap35xxPkg/Flash/Flash.c
View File

@ -271,7 +271,7 @@ NandCalculateEcc (
for (Index = 0; Index < gNum512BytesChunks; Index++) { for (Index = 0; Index < gNum512BytesChunks; Index++) {
EccResult = MmioRead32(EccResultRegister); EccResult = MmioRead32 (EccResultRegister);
//Calculate ECC code from 32-bit ECC result value. //Calculate ECC code from 32-bit ECC result value.
//NOTE: Following calculation is not part of TRM. We got this information //NOTE: Following calculation is not part of TRM. We got this information

4
Omap35xxPkg/Flash/Flash.h
View File

@ -74,10 +74,10 @@
//Nand status register bit definition //Nand status register bit definition
#define NAND_SUCCESS (0x0UL << 0) #define NAND_SUCCESS (0x0UL << 0)
#define NAND_FAILURE (0x1UL << 0) #define NAND_FAILURE BIT0
#define NAND_BUSY (0x0UL << 6) #define NAND_BUSY (0x0UL << 6)
#define NAND_READY (0x1UL << 6) #define NAND_READY BIT6
#define NAND_RESET_STATUS (0x60UL << 0) #define NAND_RESET_STATUS (0x60UL << 0)

2
Omap35xxPkg/Flash/Flash.inf
View File

@ -42,7 +42,7 @@
gEfiCpuArchProtocolGuid gEfiCpuArchProtocolGuid
[Pcd] [Pcd]
gOmap35xxTokenSpaceGuid.PcdBeagleGpmcOffset gOmap35xxTokenSpaceGuid.PcdOmap35xxGpmcOffset
[depex] [depex]
TRUE TRUE

2
Omap35xxPkg/Gpio/Gpio.c
View File

@ -43,7 +43,7 @@ Get (
DataInRegister = GpioBase(Port) + GPIO_DATAIN; DataInRegister = GpioBase(Port) + GPIO_DATAIN;
if (MmioRead32(DataInRegister) & GPIO_DATAIN_MASK(Pin)) { if (MmioRead32 (DataInRegister) & GPIO_DATAIN_MASK(Pin)) {
*Value = 1; *Value = 1;
} else { } else {
*Value = 0; *Value = 0;

10
Omap35xxPkg/Include/Omap3530/Omap3530.h
View File

@ -28,11 +28,11 @@
//CONTROL_PBIAS_LITE //CONTROL_PBIAS_LITE
#define CONTROL_PBIAS_LITE 0x48002520 #define CONTROL_PBIAS_LITE 0x48002520
#define PBIASLITEVMODE0 (0x1UL << 0) #define PBIASLITEVMODE0 BIT0
#define PBIASLITEPWRDNZ0 (0x1UL << 1) #define PBIASLITEPWRDNZ0 BIT1
#define PBIASSPEEDCTRL0 (0x1UL << 2) #define PBIASSPEEDCTRL0 BIT2
#define PBIASLITEVMODE1 (0x1UL << 8) #define PBIASLITEVMODE1 BIT8
#define PBIASLITEWRDNZ1 (0x1UL << 9) #define PBIASLITEWRDNZ1 BIT9
#endif // __OMAP3530_H__ #endif // __OMAP3530_H__

24
Omap35xxPkg/Include/Omap3530/Omap3530Gpio.h
View File

@ -50,21 +50,21 @@
#define GPIO_SYSCONFIG_IDLEMODE_MASK (3UL << 3) #define GPIO_SYSCONFIG_IDLEMODE_MASK (3UL << 3)
#define GPIO_SYSCONFIG_IDLEMODE_FORCE (0UL << 3) #define GPIO_SYSCONFIG_IDLEMODE_FORCE (0UL << 3)
#define GPIO_SYSCONFIG_IDLEMODE_NONE (1UL << 3) #define GPIO_SYSCONFIG_IDLEMODE_NONE BIT3
#define GPIO_SYSCONFIG_IDLEMODE_SMART (2UL << 3) #define GPIO_SYSCONFIG_IDLEMODE_SMART (2UL << 3)
#define GPIO_SYSCONFIG_ENAWAKEUP_MASK (1UL << 2) #define GPIO_SYSCONFIG_ENAWAKEUP_MASK BIT2
#define GPIO_SYSCONFIG_ENAWAKEUP_DISABLE (0UL << 2) #define GPIO_SYSCONFIG_ENAWAKEUP_DISABLE (0UL << 2)
#define GPIO_SYSCONFIG_ENAWAKEUP_ENABLE (1UL << 2) #define GPIO_SYSCONFIG_ENAWAKEUP_ENABLE BIT2
#define GPIO_SYSCONFIG_SOFTRESET_MASK (1UL << 1) #define GPIO_SYSCONFIG_SOFTRESET_MASK BIT1
#define GPIO_SYSCONFIG_SOFTRESET_NORMAL (0UL << 1) #define GPIO_SYSCONFIG_SOFTRESET_NORMAL (0UL << 1)
#define GPIO_SYSCONFIG_SOFTRESET_RESET (1UL << 1) #define GPIO_SYSCONFIG_SOFTRESET_RESET BIT1
#define GPIO_SYSCONFIG_AUTOIDLE_MASK (1UL << 0) #define GPIO_SYSCONFIG_AUTOIDLE_MASK BIT0
#define GPIO_SYSCONFIG_AUTOIDLE_FREE_RUN (0UL << 0) #define GPIO_SYSCONFIG_AUTOIDLE_FREE_RUN (0UL << 0)
#define GPIO_SYSCONFIG_AUTOIDLE_ON (1UL << 0) #define GPIO_SYSCONFIG_AUTOIDLE_ON BIT0
#define GPIO_SYSSTATUS_RESETDONE_MASK (1UL << 0) #define GPIO_SYSSTATUS_RESETDONE_MASK BIT0
#define GPIO_SYSSTATUS_RESETDONE_ONGOING (0UL << 0) #define GPIO_SYSSTATUS_RESETDONE_ONGOING (0UL << 0)
#define GPIO_SYSSTATUS_RESETDONE_COMPLETE (1UL << 0) #define GPIO_SYSSTATUS_RESETDONE_COMPLETE BIT0
#define GPIO_IRQSTATUS_MASK(x) (1UL << (x)) #define GPIO_IRQSTATUS_MASK(x) (1UL << (x))
#define GPIO_IRQSTATUS_NOT_TRIGGERED(x) (0UL << (x)) #define GPIO_IRQSTATUS_NOT_TRIGGERED(x) (0UL << (x))
@ -81,12 +81,12 @@
#define GPIO_CTRL_GATINGRATIO_MASK (3UL << 1) #define GPIO_CTRL_GATINGRATIO_MASK (3UL << 1)
#define GPIO_CTRL_GATINGRATIO_DIV_1 (0UL << 1) #define GPIO_CTRL_GATINGRATIO_DIV_1 (0UL << 1)
#define GPIO_CTRL_GATINGRATIO_DIV_2 (1UL << 1) #define GPIO_CTRL_GATINGRATIO_DIV_2 BIT1
#define GPIO_CTRL_GATINGRATIO_DIV_4 (2UL << 1) #define GPIO_CTRL_GATINGRATIO_DIV_4 (2UL << 1)
#define GPIO_CTRL_GATINGRATIO_DIV_8 (3UL << 1) #define GPIO_CTRL_GATINGRATIO_DIV_8 (3UL << 1)
#define GPIO_CTRL_DISABLEMODULE_MASK (1UL << 0) #define GPIO_CTRL_DISABLEMODULE_MASK BIT0
#define GPIO_CTRL_DISABLEMODULE_ENABLE (0UL << 0) #define GPIO_CTRL_DISABLEMODULE_ENABLE (0UL << 0)
#define GPIO_CTRL_DISABLEMODULE_DISABLE (1UL << 0) #define GPIO_CTRL_DISABLEMODULE_DISABLE BIT0
#define GPIO_OE_MASK(x) (1UL << (x)) #define GPIO_OE_MASK(x) (1UL << (x))
#define GPIO_OE_OUTPUT(x) (0UL << (x)) #define GPIO_OE_OUTPUT(x) (0UL << (x))

26
Omap35xxPkg/Include/Omap3530/Omap3530Gpmc.h
View File

@ -26,14 +26,14 @@
#define GPMC_IRQENABLE (GPMC_BASE + 0x1C) #define GPMC_IRQENABLE (GPMC_BASE + 0x1C)
#define GPMC_TIMEOUT_CONTROL (GPMC_BASE + 0x40) #define GPMC_TIMEOUT_CONTROL (GPMC_BASE + 0x40)
#define TIMEOUTENABLE (0x1UL << 0) #define TIMEOUTENABLE BIT0
#define TIMEOUTDISABLE (0x0UL << 0) #define TIMEOUTDISABLE (0x0UL << 0)
#define GPMC_ERR_ADDRESS (GPMC_BASE + 0x44) #define GPMC_ERR_ADDRESS (GPMC_BASE + 0x44)
#define GPMC_ERR_TYPE (GPMC_BASE + 0x48) #define GPMC_ERR_TYPE (GPMC_BASE + 0x48)
#define GPMC_CONFIG (GPMC_BASE + 0x50) #define GPMC_CONFIG (GPMC_BASE + 0x50)
#define WRITEPROTECT_HIGH (0x1UL << 4) #define WRITEPROTECT_HIGH BIT4
#define WRITEPROTECT_LOW (0x0UL << 4) #define WRITEPROTECT_LOW (0x0UL << 4)
#define GPMC_STATUS (GPMC_BASE + 0x54) #define GPMC_STATUS (GPMC_BASE + 0x54)
@ -42,7 +42,7 @@
#define DEVICETYPE_NOR (0x0UL << 10) #define DEVICETYPE_NOR (0x0UL << 10)
#define DEVICETYPE_NAND (0x2UL << 10) #define DEVICETYPE_NAND (0x2UL << 10)
#define DEVICESIZE_X8 (0x0UL << 12) #define DEVICESIZE_X8 (0x0UL << 12)
#define DEVICESIZE_X16 (0x1UL << 12) #define DEVICESIZE_X16 BIT12
#define GPMC_CONFIG2_0 (GPMC_BASE + 0x64) #define GPMC_CONFIG2_0 (GPMC_BASE + 0x64)
#define CSONTIME (0x0UL << 0) #define CSONTIME (0x0UL << 0)
@ -54,26 +54,26 @@
#define ADVWROFFTIME (0x14UL << 16) #define ADVWROFFTIME (0x14UL << 16)
#define GPMC_CONFIG4_0 (GPMC_BASE + 0x6C) #define GPMC_CONFIG4_0 (GPMC_BASE + 0x6C)
#define OEONTIME (0x1UL << 0) #define OEONTIME BIT0
#define OEOFFTIME (0xFUL << 8) #define OEOFFTIME (0xFUL << 8)
#define WEONTIME (0x1UL << 16) #define WEONTIME BIT16
#define WEOFFTIME (0xFUL << 24) #define WEOFFTIME (0xFUL << 24)
#define GPMC_CONFIG5_0 (GPMC_BASE + 0x70) #define GPMC_CONFIG5_0 (GPMC_BASE + 0x70)
#define RDCYCLETIME (0x14UL << 0) #define RDCYCLETIME (0x14UL << 0)
#define WRCYCLETIME (0x14UL << 8) #define WRCYCLETIME (0x14UL << 8)
#define RDACCESSTIME (0xCUL << 16) #define RDACCESSTIME (0xCUL << 16)
#define PAGEBURSTACCESSTIME (0x1UL << 24) #define PAGEBURSTACCESSTIME BIT24
#define GPMC_CONFIG6_0 (GPMC_BASE + 0x74) #define GPMC_CONFIG6_0 (GPMC_BASE + 0x74)
#define CYCLE2CYCLESAMECSEN (0x1UL << 7) #define CYCLE2CYCLESAMECSEN BIT7
#define CYCLE2CYCLEDELAY (0xAUL << 8) #define CYCLE2CYCLEDELAY (0xAUL << 8)
#define WRDATAONADMUXBUS (0xFUL << 16) #define WRDATAONADMUXBUS (0xFUL << 16)
#define WRACCESSTIME (0x1FUL << 24) #define WRACCESSTIME BIT24
#define GPMC_CONFIG7_0 (GPMC_BASE + 0x78) #define GPMC_CONFIG7_0 (GPMC_BASE + 0x78)
#define BASEADDRESS (0x30UL << 0) #define BASEADDRESS (0x30UL << 0)
#define CSVALID (0x1UL << 6) #define CSVALID BIT6
#define MASKADDRESS_128MB (0x8UL << 8) #define MASKADDRESS_128MB (0x8UL << 8)
#define GPMC_NAND_COMMAND_0 (GPMC_BASE + 0x7C) #define GPMC_NAND_COMMAND_0 (GPMC_BASE + 0x7C)
@ -81,14 +81,14 @@
#define GPMC_NAND_DATA_0 (GPMC_BASE + 0x84) #define GPMC_NAND_DATA_0 (GPMC_BASE + 0x84)
#define GPMC_ECC_CONFIG (GPMC_BASE + 0x1F4) #define GPMC_ECC_CONFIG (GPMC_BASE + 0x1F4)
#define ECCENABLE (0x1UL << 0) #define ECCENABLE BIT0
#define ECCDISABLE (0x0UL << 0) #define ECCDISABLE (0x0UL << 0)
#define ECCCS_0 (0x0UL << 1) #define ECCCS_0 (0x0UL << 1)
#define ECC16B (0x1UL << 7) #define ECC16B BIT7
#define GPMC_ECC_CONTROL (GPMC_BASE + 0x1F8) #define GPMC_ECC_CONTROL (GPMC_BASE + 0x1F8)
#define ECCPOINTER_REG1 (0x1UL << 0) #define ECCPOINTER_REG1 BIT0
#define ECCCLEAR (0x1UL << 8) #define ECCCLEAR BIT8
#define GPMC_ECC_SIZE_CONFIG (GPMC_BASE + 0x1FC) #define GPMC_ECC_SIZE_CONFIG (GPMC_BASE + 0x1FC)
#define ECCSIZE0_512BYTES (0xFFUL << 12) #define ECCSIZE0_512BYTES (0xFFUL << 12)

30
Omap35xxPkg/Include/Omap3530/Omap3530I2c.h
View File

@ -19,17 +19,17 @@
#define I2C1BASE 0x48070000 #define I2C1BASE 0x48070000
#define I2C_IE (I2C1BASE + 0x4) #define I2C_IE (I2C1BASE + 0x4)
#define XRDY_IE (0x1UL << 4) #define XRDY_IE BIT4
#define RRDY_IE (0x1UL << 3) #define RRDY_IE BIT3
#define ARDY_IE (0x1UL << 2) #define ARDY_IE BIT2
#define NACK_IE (0x1UL << 1) #define NACK_IE BIT1
#define I2C_STAT (I2C1BASE + 0x8) #define I2C_STAT (I2C1BASE + 0x8)
#define BB (0x1UL << 12) #define BB BIT12
#define XRDY (0x1UL << 4) #define XRDY BIT4
#define RRDY (0x1UL << 3) #define RRDY BIT3
#define ARDY (0x1UL << 2) #define ARDY BIT2
#define NACK (0x1UL << 1) #define NACK BIT1
#define I2C_WE (I2C1BASE + 0xC) #define I2C_WE (I2C1BASE + 0xC)
#define I2C_SYSS (I2C1BASE + 0x10) #define I2C_SYSS (I2C1BASE + 0x10)
@ -39,12 +39,12 @@
#define I2C_SYSC (I2C1BASE + 0x20) #define I2C_SYSC (I2C1BASE + 0x20)
#define I2C_CON (I2C1BASE + 0x24) #define I2C_CON (I2C1BASE + 0x24)
#define STT (0x1UL << 0) #define STT BIT0
#define STP (0x1UL << 1) #define STP BIT1
#define XSA (0x1UL << 8) #define XSA BIT8
#define TRX (0x1UL << 9) #define TRX BIT9
#define MST (0x1UL << 10) #define MST BIT10
#define I2C_EN (0x1UL << 15) #define I2C_EN BIT15
#define I2C_OA0 (I2C1BASE + 0x28) #define I2C_OA0 (I2C1BASE + 0x28)
#define I2C_SA (I2C1BASE + 0x2C) #define I2C_SA (I2C1BASE + 0x2C)

3
Omap35xxPkg/Include/Omap3530/Omap3530Interrupt.h
View File

@ -40,7 +40,8 @@
#define INTCPS_ILR(m) (INTERRUPT_BASE + 0x0100 + (0x04 * (m))) #define INTCPS_ILR(m) (INTERRUPT_BASE + 0x0100 + (0x04 * (m)))
#define INTCPS_SIR_IRQ_MASK (0x7F) #define INTCPS_SIR_IRQ_MASK (0x7F)
#define INTCPS_CONTROL_NEWIRQAGR (1UL << 0) #define INTCPS_CONTROL_NEWIRQAGR BIT0
#define INTCPS_CONTROL_NEWFIQAGR BIT1
#endif // __OMAP3530INTERRUPT_H__ #endif // __OMAP3530INTERRUPT_H__

156
Omap35xxPkg/Include/Omap3530/Omap3530MMCHS.h
View File

@ -20,31 +20,31 @@
#define MMC_REFERENCE_CLK (96000000) #define MMC_REFERENCE_CLK (96000000)
#define MMCHS_SYSCONFIG (MMCHS1BASE + 0x10) #define MMCHS_SYSCONFIG (MMCHS1BASE + 0x10)
#define SOFTRESET (0x1UL << 1) #define SOFTRESET BIT1
#define ENAWAKEUP (0x1UL << 2) #define ENAWAKEUP BIT2
#define MMCHS_SYSSTATUS (MMCHS1BASE + 0x14) #define MMCHS_SYSSTATUS (MMCHS1BASE + 0x14)
#define RESETDONE_MASK (0x1UL << 0) #define RESETDONE_MASK BIT0
#define RESETDONE (0x1UL << 0) #define RESETDONE BIT0
#define MMCHS_CSRE (MMCHS1BASE + 0x24) #define MMCHS_CSRE (MMCHS1BASE + 0x24)
#define MMCHS_SYSTEST (MMCHS1BASE + 0x28) #define MMCHS_SYSTEST (MMCHS1BASE + 0x28)
#define MMCHS_CON (MMCHS1BASE + 0x2C) #define MMCHS_CON (MMCHS1BASE + 0x2C)
#define OD (0x1UL << 0) #define OD BIT0
#define NOINIT (0x0UL << 1) #define NOINIT (0x0UL << 1)
#define INIT (0x1UL << 1) #define INIT BIT1
#define HR (0x1UL << 2) #define HR BIT2
#define STR (0x1UL << 3) #define STR BIT3
#define MODE (0x1UL << 4) #define MODE BIT4
#define DW8_1_4_BIT (0x0UL << 5) #define DW8_1_4_BIT (0x0UL << 5)
#define DW8_8_BIT (0x1UL << 5) #define DW8_8_BIT BIT5
#define MIT (0x1UL << 6) #define MIT BIT6
#define CDP (0x1UL << 7) #define CDP BIT7
#define WPP (0x1UL << 8) #define WPP BIT8
#define CTPL (0x1UL << 11) #define CTPL BIT11
#define CEATA_OFF (0x0UL << 12) #define CEATA_OFF (0x0UL << 12)
#define CEATA_ON (0x1UL << 12) #define CEATA_ON BIT12
#define MMCHS_PWCNT (MMCHS1BASE + 0x30) #define MMCHS_PWCNT (MMCHS1BASE + 0x30)
@ -54,19 +54,19 @@
#define MMCHS_ARG (MMCHS1BASE + 0x108) #define MMCHS_ARG (MMCHS1BASE + 0x108)
#define MMCHS_CMD (MMCHS1BASE + 0x10C) #define MMCHS_CMD (MMCHS1BASE + 0x10C)
#define DE_ENABLE (0x1UL << 0) #define DE_ENABLE BIT0
#define BCE_ENABLE (0x1UL << 1) #define BCE_ENABLE BIT1
#define ACEN_ENABLE (0x1UL << 2) #define ACEN_ENABLE BIT2
#define DDIR_READ (0x1UL << 4) #define DDIR_READ BIT4
#define DDIR_WRITE (0x0UL << 4) #define DDIR_WRITE (0x0UL << 4)
#define MSBS_SGLEBLK (0x0UL << 5) #define MSBS_SGLEBLK (0x0UL << 5)
#define MSBS_MULTBLK (0x1UL << 5) #define MSBS_MULTBLK BIT5
#define RSP_TYPE_MASK (0x3UL << 16) #define RSP_TYPE_MASK (0x3UL << 16)
#define RSP_TYPE_136BITS (0x1UL << 16) #define RSP_TYPE_136BITS BIT16
#define RSP_TYPE_48BITS (0x2UL << 16) #define RSP_TYPE_48BITS (0x2UL << 16)
#define CCCE_ENABLE (0x1UL << 19) #define CCCE_ENABLE BIT19
#define CICE_ENABLE (0x1UL << 20) #define CICE_ENABLE BIT20
#define DP_ENABLE (0x1UL << 21) #define DP_ENABLE BIT21
#define INDX(CMD_INDX) ((CMD_INDX & 0x3F) << 24) #define INDX(CMD_INDX) ((CMD_INDX & 0x3F) << 24)
#define MMCHS_RSP10 (MMCHS1BASE + 0x110) #define MMCHS_RSP10 (MMCHS1BASE + 0x110)
@ -76,84 +76,84 @@
#define MMCHS_DATA (MMCHS1BASE + 0x120) #define MMCHS_DATA (MMCHS1BASE + 0x120)
#define MMCHS_PSTATE (MMCHS1BASE + 0x124) #define MMCHS_PSTATE (MMCHS1BASE + 0x124)
#define CMDI_MASK (0x1UL << 0) #define CMDI_MASK BIT0
#define CMDI_ALLOWED (0x0UL << 0) #define CMDI_ALLOWED (0x0UL << 0)
#define CMDI_NOT_ALLOWED (0x1UL << 0) #define CMDI_NOT_ALLOWED BIT0
#define DATI_MASK (0x1UL << 1) #define DATI_MASK BIT1
#define DATI_ALLOWED (0x0UL << 1) #define DATI_ALLOWED (0x0UL << 1)
#define DATI_NOT_ALLOWED (0x1UL << 1) #define DATI_NOT_ALLOWED BIT1
#define MMCHS_HCTL (MMCHS1BASE + 0x128) #define MMCHS_HCTL (MMCHS1BASE + 0x128)
#define DTW_1_BIT (0x0UL << 1) #define DTW_1_BIT (0x0UL << 1)
#define DTW_4_BIT (0x1UL << 1) #define DTW_4_BIT BIT1
#define SDBP_MASK (0x1UL << 8) #define SDBP_MASK BIT8
#define SDBP_OFF (0x0UL << 8) #define SDBP_OFF (0x0UL << 8)
#define SDBP_ON (0x1UL << 8) #define SDBP_ON BIT8
#define SDVS_1_8_V (0x5UL << 9) #define SDVS_1_8_V (0x5UL << 9)
#define SDVS_3_0_V (0x6UL << 9) #define SDVS_3_0_V (0x6UL << 9)
#define IWE (0x1UL << 24) #define IWE BIT24
#define MMCHS_SYSCTL (MMCHS1BASE + 0x12C) #define MMCHS_SYSCTL (MMCHS1BASE + 0x12C)
#define ICE (0x1UL << 0) #define ICE BIT0
#define ICS_MASK (0x1UL << 1) #define ICS_MASK BIT1
#define ICS (0x1UL << 1) #define ICS BIT1
#define CEN (0x1UL << 2) #define CEN BIT2
#define CLKD_MASK (0x3FFUL << 6) #define CLKD_MASK (0x3FFUL << 6)
#define CLKD_80KHZ (0x258UL) //(96*1000/80)/2 #define CLKD_80KHZ (0x258UL) //(96*1000/80)/2
#define CLKD_400KHZ (0xF0UL) #define CLKD_400KHZ (0xF0UL)
#define DTO_MASK (0xFUL << 16) #define DTO_MASK (0xFUL << 16)
#define DTO_VAL (0xEUL << 16) #define DTO_VAL (0xEUL << 16)
#define SRA (0x1UL << 24) #define SRA BIT24
#define SRC_MASK (0x1UL << 25) #define SRC_MASK BIT25
#define SRC (0x1UL << 25) #define SRC BIT25
#define SRD (0x1UL << 26) #define SRD BIT26
#define MMCHS_STAT (MMCHS1BASE + 0x130) #define MMCHS_STAT (MMCHS1BASE + 0x130)
#define CC (0x1UL << 0) #define CC BIT0
#define TC (0x1UL << 1) #define TC BIT1
#define BWR (0x1UL << 4) #define BWR BIT4
#define BRR (0x1UL << 5) #define BRR BIT5
#define ERRI (0x1UL << 15) #define ERRI BIT15
#define CTO (0x1UL << 16) #define CTO BIT16
#define DTO (0x1UL << 20) #define DTO BIT20
#define DCRC (0x1UL << 21) #define DCRC BIT21
#define DEB (0x1UL << 22) #define DEB BIT22
#define MMCHS_IE (MMCHS1BASE + 0x134) #define MMCHS_IE (MMCHS1BASE + 0x134)
#define CC_EN (0x1UL << 0) #define CC_EN BIT0
#define TC_EN (0x1UL << 1) #define TC_EN BIT1
#define BWR_EN (0x1UL << 4) #define BWR_EN BIT4
#define BRR_EN (0x1UL << 5) #define BRR_EN BIT5
#define CTO_EN (0x1UL << 16) #define CTO_EN BIT16
#define CCRC_EN (0x1UL << 17) #define CCRC_EN BIT17
#define CEB_EN (0x1UL << 18) #define CEB_EN BIT18
#define CIE_EN (0x1UL << 19) #define CIE_EN BIT19
#define DTO_EN (0x1UL << 20) #define DTO_EN BIT20
#define DCRC_EN (0x1UL << 21) #define DCRC_EN BIT21
#define DEB_EN (0x1UL << 22) #define DEB_EN BIT22
#define CERR_EN (0x1UL << 28) #define CERR_EN BIT28
#define BADA_EN (0x1UL << 29) #define BADA_EN BIT29
#define MMCHS_ISE (MMCHS1BASE + 0x138) #define MMCHS_ISE (MMCHS1BASE + 0x138)
#define CC_SIGEN (0x1UL << 0) #define CC_SIGEN BIT0
#define TC_SIGEN (0x1UL << 1) #define TC_SIGEN BIT1
#define BWR_SIGEN (0x1UL << 4) #define BWR_SIGEN BIT4
#define BRR_SIGEN (0x1UL << 5) #define BRR_SIGEN BIT5
#define CTO_SIGEN (0x1UL << 16) #define CTO_SIGEN BIT16
#define CCRC_SIGEN (0x1UL << 17) #define CCRC_SIGEN BIT17
#define CEB_SIGEN (0x1UL << 18) #define CEB_SIGEN BIT18
#define CIE_SIGEN (0x1UL << 19) #define CIE_SIGEN BIT19
#define DTO_SIGEN (0x1UL << 20) #define DTO_SIGEN BIT20
#define DCRC_SIGEN (0x1UL << 21) #define DCRC_SIGEN BIT21
#define DEB_SIGEN (0x1UL << 22) #define DEB_SIGEN BIT22
#define CERR_SIGEN (0x1UL << 28) #define CERR_SIGEN BIT28
#define BADA_SIGEN (0x1UL << 29) #define BADA_SIGEN BIT29
#define MMCHS_AC12 (MMCHS1BASE + 0x13C) #define MMCHS_AC12 (MMCHS1BASE + 0x13C)
#define MMCHS_CAPA (MMCHS1BASE + 0x140) #define MMCHS_CAPA (MMCHS1BASE + 0x140)
#define VS30 (0x1UL << 25) #define VS30 BIT25
#define VS18 (0x1UL << 26) #define VS18 BIT26
#define MMCHS_CUR_CAPA (MMCHS1BASE + 0x148) #define MMCHS_CUR_CAPA (MMCHS1BASE + 0x148)
#define MMCHS_REV (MMCHS1BASE + 0x1FC) #define MMCHS_REV (MMCHS1BASE + 0x1FC)
@ -179,7 +179,7 @@
#define CMD8 (INDX(8) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS) #define CMD8 (INDX(8) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
#define CMD8_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN) #define CMD8_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)
//Reserved(0)[12:31], Supply voltage(1)[11:8], check pattern(0xCE)[7:0] = 0x1CE //Reserved(0)[12:31], Supply voltage(1)[11:8], check pattern(0xCE)[7:0] = 0x1CE
#define CMD8_ARG (0x0UL << 12 | 0x1UL << 8 | 0xCEUL << 0) #define CMD8_ARG (0x0UL << 12 | BIT8 | 0xCEUL << 0)
#define CMD9 (INDX(9) | CCCE_ENABLE | RSP_TYPE_136BITS) #define CMD9 (INDX(9) | CCCE_ENABLE | RSP_TYPE_136BITS)
#define CMD9_INT_EN (CCRC_EN | CC_EN | CEB_EN | CTO_EN) #define CMD9_INT_EN (CCRC_EN | CC_EN | CEB_EN | CTO_EN)

4
Omap35xxPkg/Include/Omap3530/Omap3530PadConfiguration.h
View File

@ -281,9 +281,9 @@
#define WAKEUP_MASK (0x2UL << WAKEUP_OFFSET) #define WAKEUP_MASK (0x2UL << WAKEUP_OFFSET)
#define PULLUDDISABLE (0x0UL << 0) #define PULLUDDISABLE (0x0UL << 0)
#define PULLUDENABLE (0x1UL << 0) #define PULLUDENABLE BIT0
#define PULLTYPENOSELECT (0x0UL << 1) #define PULLTYPENOSELECT (0x0UL << 1)
#define PULLTYPESELECT (0x1UL << 1) #define PULLTYPESELECT BIT1
#define OUTPUT (0x0UL) //Pin is configured in output only mode. #define OUTPUT (0x0UL) //Pin is configured in output only mode.
#define INPUT (0x1UL) //Pin is configured in bi-directional mode. #define INPUT (0x1UL) //Pin is configured in bi-directional mode.

86
Omap35xxPkg/Include/Omap3530/Omap3530Prcm.h
View File

@ -40,29 +40,29 @@
#define PRM_RSTST (0x48307258) #define PRM_RSTST (0x48307258)
//CORE clock //CORE clock
#define CM_FCLKEN1_CORE_EN_I2C1_MASK (1UL << 15) #define CM_FCLKEN1_CORE_EN_I2C1_MASK BIT15
#define CM_FCLKEN1_CORE_EN_I2C1_DISABLE (0UL << 15) #define CM_FCLKEN1_CORE_EN_I2C1_DISABLE (0UL << 15)
#define CM_FCLKEN1_CORE_EN_I2C1_ENABLE (1UL << 15) #define CM_FCLKEN1_CORE_EN_I2C1_ENABLE BIT15
#define CM_ICLKEN1_CORE_EN_I2C1_MASK (1UL << 15) #define CM_ICLKEN1_CORE_EN_I2C1_MASK BIT15
#define CM_ICLKEN1_CORE_EN_I2C1_DISABLE (0UL << 15) #define CM_ICLKEN1_CORE_EN_I2C1_DISABLE (0UL << 15)
#define CM_ICLKEN1_CORE_EN_I2C1_ENABLE (1UL << 15) #define CM_ICLKEN1_CORE_EN_I2C1_ENABLE BIT15
#define CM_FCLKEN1_CORE_EN_MMC1_MASK (1UL << 24) #define CM_FCLKEN1_CORE_EN_MMC1_MASK BIT24
#define CM_FCLKEN1_CORE_EN_MMC1_DISABLE (0UL << 24) #define CM_FCLKEN1_CORE_EN_MMC1_DISABLE (0UL << 24)
#define CM_FCLKEN1_CORE_EN_MMC1_ENABLE (1UL << 24) #define CM_FCLKEN1_CORE_EN_MMC1_ENABLE BIT24
#define CM_FCLKEN3_CORE_EN_USBTLL_MASK (1UL << 2) #define CM_FCLKEN3_CORE_EN_USBTLL_MASK BIT2
#define CM_FCLKEN3_CORE_EN_USBTLL_DISABLE (0UL << 2) #define CM_FCLKEN3_CORE_EN_USBTLL_DISABLE (0UL << 2)
#define CM_FCLKEN3_CORE_EN_USBTLL_ENABLE (1UL << 2) #define CM_FCLKEN3_CORE_EN_USBTLL_ENABLE BIT2
#define CM_ICLKEN1_CORE_EN_MMC1_MASK (1UL << 24) #define CM_ICLKEN1_CORE_EN_MMC1_MASK BIT24
#define CM_ICLKEN1_CORE_EN_MMC1_DISABLE (0UL << 24) #define CM_ICLKEN1_CORE_EN_MMC1_DISABLE (0UL << 24)
#define CM_ICLKEN1_CORE_EN_MMC1_ENABLE (1UL << 24) #define CM_ICLKEN1_CORE_EN_MMC1_ENABLE BIT24
#define CM_ICLKEN3_CORE_EN_USBTLL_MASK (1UL << 2) #define CM_ICLKEN3_CORE_EN_USBTLL_MASK BIT2
#define CM_ICLKEN3_CORE_EN_USBTLL_DISABLE (0UL << 2) #define CM_ICLKEN3_CORE_EN_USBTLL_DISABLE (0UL << 2)
#define CM_ICLKEN3_CORE_EN_USBTLL_ENABLE (1UL << 2) #define CM_ICLKEN3_CORE_EN_USBTLL_ENABLE BIT2
#define CM_CLKEN_FREQSEL_075_100 (0x03UL << 4) #define CM_CLKEN_FREQSEL_075_100 (0x03UL << 4)
#define CM_CLKEN_ENABLE (7UL << 0) #define CM_CLKEN_ENABLE (7UL << 0)
@ -72,93 +72,93 @@
#define CM_CLKSEL_DIV_120M(x) (((x) & 0x1F) << 0) #define CM_CLKSEL_DIV_120M(x) (((x) & 0x1F) << 0)
#define CM_FCLKEN_USBHOST_EN_USBHOST2_MASK (1UL << 1) #define CM_FCLKEN_USBHOST_EN_USBHOST2_MASK BIT1
#define CM_FCLKEN_USBHOST_EN_USBHOST2_DISABLE (0UL << 1) #define CM_FCLKEN_USBHOST_EN_USBHOST2_DISABLE (0UL << 1)
#define CM_FCLKEN_USBHOST_EN_USBHOST2_ENABLE (1UL << 1) #define CM_FCLKEN_USBHOST_EN_USBHOST2_ENABLE BIT1
#define CM_FCLKEN_USBHOST_EN_USBHOST1_MASK (1UL << 0) #define CM_FCLKEN_USBHOST_EN_USBHOST1_MASK BIT0
#define CM_FCLKEN_USBHOST_EN_USBHOST1_DISABLE (0UL << 0) #define CM_FCLKEN_USBHOST_EN_USBHOST1_DISABLE (0UL << 0)
#define CM_FCLKEN_USBHOST_EN_USBHOST1_ENABLE (1UL << 0) #define CM_FCLKEN_USBHOST_EN_USBHOST1_ENABLE BIT0
#define CM_ICLKEN_USBHOST_EN_USBHOST_MASK (1UL << 0) #define CM_ICLKEN_USBHOST_EN_USBHOST_MASK BIT0
#define CM_ICLKEN_USBHOST_EN_USBHOST_DISABLE (0UL << 0) #define CM_ICLKEN_USBHOST_EN_USBHOST_DISABLE (0UL << 0)
#define CM_ICLKEN_USBHOST_EN_USBHOST_ENABLE (1UL << 0) #define CM_ICLKEN_USBHOST_EN_USBHOST_ENABLE BIT0
//Wakeup functional clock //Wakeup functional clock
#define CM_FCLKEN_WKUP_EN_GPIO1_DISABLE (0UL << 3) #define CM_FCLKEN_WKUP_EN_GPIO1_DISABLE (0UL << 3)
#define CM_FCLKEN_WKUP_EN_GPIO1_ENABLE (1UL << 3) #define CM_FCLKEN_WKUP_EN_GPIO1_ENABLE BIT3
#define CM_FCLKEN_WKUP_EN_WDT2_DISABLE (0UL << 5) #define CM_FCLKEN_WKUP_EN_WDT2_DISABLE (0UL << 5)
#define CM_FCLKEN_WKUP_EN_WDT2_ENABLE (1UL << 5) #define CM_FCLKEN_WKUP_EN_WDT2_ENABLE BIT5
//Wakeup interface clock //Wakeup interface clock
#define CM_ICLKEN_WKUP_EN_GPIO1_DISABLE (0UL << 3) #define CM_ICLKEN_WKUP_EN_GPIO1_DISABLE (0UL << 3)
#define CM_ICLKEN_WKUP_EN_GPIO1_ENABLE (1UL << 3) #define CM_ICLKEN_WKUP_EN_GPIO1_ENABLE BIT3
#define CM_ICLKEN_WKUP_EN_WDT2_DISABLE (0UL << 5) #define CM_ICLKEN_WKUP_EN_WDT2_DISABLE (0UL << 5)
#define CM_ICLKEN_WKUP_EN_WDT2_ENABLE (1UL << 5) #define CM_ICLKEN_WKUP_EN_WDT2_ENABLE BIT5
//Peripheral functional clock //Peripheral functional clock
#define CM_FCLKEN_PER_EN_GPT3_DISABLE (0UL << 4) #define CM_FCLKEN_PER_EN_GPT3_DISABLE (0UL << 4)
#define CM_FCLKEN_PER_EN_GPT3_ENABLE (1UL << 4) #define CM_FCLKEN_PER_EN_GPT3_ENABLE BIT4
#define CM_FCLKEN_PER_EN_GPT4_DISABLE (0UL << 5) #define CM_FCLKEN_PER_EN_GPT4_DISABLE (0UL << 5)
#define CM_FCLKEN_PER_EN_GPT4_ENABLE (1UL << 5) #define CM_FCLKEN_PER_EN_GPT4_ENABLE BIT5
#define CM_FCLKEN_PER_EN_UART3_DISABLE (0UL << 11) #define CM_FCLKEN_PER_EN_UART3_DISABLE (0UL << 11)
#define CM_FCLKEN_PER_EN_UART3_ENABLE (1UL << 11) #define CM_FCLKEN_PER_EN_UART3_ENABLE BIT11
#define CM_FCLKEN_PER_EN_GPIO2_DISABLE (0UL << 13) #define CM_FCLKEN_PER_EN_GPIO2_DISABLE (0UL << 13)
#define CM_FCLKEN_PER_EN_GPIO2_ENABLE (1UL << 13) #define CM_FCLKEN_PER_EN_GPIO2_ENABLE BIT13
#define CM_FCLKEN_PER_EN_GPIO3_DISABLE (0UL << 14) #define CM_FCLKEN_PER_EN_GPIO3_DISABLE (0UL << 14)
#define CM_FCLKEN_PER_EN_GPIO3_ENABLE (1UL << 14) #define CM_FCLKEN_PER_EN_GPIO3_ENABLE BIT14
#define CM_FCLKEN_PER_EN_GPIO4_DISABLE (0UL << 15) #define CM_FCLKEN_PER_EN_GPIO4_DISABLE (0UL << 15)
#define CM_FCLKEN_PER_EN_GPIO4_ENABLE (1UL << 15) #define CM_FCLKEN_PER_EN_GPIO4_ENABLE BIT15
#define CM_FCLKEN_PER_EN_GPIO5_DISABLE (0UL << 16) #define CM_FCLKEN_PER_EN_GPIO5_DISABLE (0UL << 16)
#define CM_FCLKEN_PER_EN_GPIO5_ENABLE (1UL << 16) #define CM_FCLKEN_PER_EN_GPIO5_ENABLE BIT16
#define CM_FCLKEN_PER_EN_GPIO6_DISABLE (0UL << 17) #define CM_FCLKEN_PER_EN_GPIO6_DISABLE (0UL << 17)
#define CM_FCLKEN_PER_EN_GPIO6_ENABLE (1UL << 17) #define CM_FCLKEN_PER_EN_GPIO6_ENABLE BIT17
//Peripheral interface clock //Peripheral interface clock
#define CM_ICLKEN_PER_EN_GPT3_DISABLE (0UL << 4) #define CM_ICLKEN_PER_EN_GPT3_DISABLE (0UL << 4)
#define CM_ICLKEN_PER_EN_GPT3_ENABLE (1UL << 4) #define CM_ICLKEN_PER_EN_GPT3_ENABLE BIT4
#define CM_ICLKEN_PER_EN_GPT4_DISABLE (0UL << 5) #define CM_ICLKEN_PER_EN_GPT4_DISABLE (0UL << 5)
#define CM_ICLKEN_PER_EN_GPT4_ENABLE (1UL << 5) #define CM_ICLKEN_PER_EN_GPT4_ENABLE BIT5
#define CM_ICLKEN_PER_EN_UART3_DISABLE (0UL << 11) #define CM_ICLKEN_PER_EN_UART3_DISABLE (0UL << 11)
#define CM_ICLKEN_PER_EN_UART3_ENABLE (1UL << 11) #define CM_ICLKEN_PER_EN_UART3_ENABLE BIT11
#define CM_ICLKEN_PER_EN_GPIO2_DISABLE (0UL << 13) #define CM_ICLKEN_PER_EN_GPIO2_DISABLE (0UL << 13)
#define CM_ICLKEN_PER_EN_GPIO2_ENABLE (1UL << 13) #define CM_ICLKEN_PER_EN_GPIO2_ENABLE BIT13
#define CM_ICLKEN_PER_EN_GPIO3_DISABLE (0UL << 14) #define CM_ICLKEN_PER_EN_GPIO3_DISABLE (0UL << 14)
#define CM_ICLKEN_PER_EN_GPIO3_ENABLE (1UL << 14) #define CM_ICLKEN_PER_EN_GPIO3_ENABLE BIT14
#define CM_ICLKEN_PER_EN_GPIO4_DISABLE (0UL << 15) #define CM_ICLKEN_PER_EN_GPIO4_DISABLE (0UL << 15)
#define CM_ICLKEN_PER_EN_GPIO4_ENABLE (1UL << 15) #define CM_ICLKEN_PER_EN_GPIO4_ENABLE BIT15
#define CM_ICLKEN_PER_EN_GPIO5_DISABLE (0UL << 16) #define CM_ICLKEN_PER_EN_GPIO5_DISABLE (0UL << 16)
#define CM_ICLKEN_PER_EN_GPIO5_ENABLE (1UL << 16) #define CM_ICLKEN_PER_EN_GPIO5_ENABLE BIT16
#define CM_ICLKEN_PER_EN_GPIO6_DISABLE (0UL << 17) #define CM_ICLKEN_PER_EN_GPIO6_DISABLE (0UL << 17)
#define CM_ICLKEN_PER_EN_GPIO6_ENABLE (1UL << 17) #define CM_ICLKEN_PER_EN_GPIO6_ENABLE BIT17
//Timer source clock selection //Timer source clock selection
#define CM_CLKSEL_PER_CLKSEL_GPT3_32K (0UL << 1) #define CM_CLKSEL_PER_CLKSEL_GPT3_32K (0UL << 1)
#define CM_CLKSEL_PER_CLKSEL_GPT3_SYS (1UL << 1) #define CM_CLKSEL_PER_CLKSEL_GPT3_SYS BIT1
#define CM_CLKSEL_PER_CLKSEL_GPT4_32K (0UL << 2) #define CM_CLKSEL_PER_CLKSEL_GPT4_32K (0UL << 2)
#define CM_CLKSEL_PER_CLKSEL_GPT4_SYS (1UL << 2) #define CM_CLKSEL_PER_CLKSEL_GPT4_SYS BIT2
//Reset management (Global and Cold reset) //Reset management (Global and Cold reset)
#define RST_GS (0x1UL << 1) #define RST_GS BIT1
#define RST_DPLL3 (0x1UL << 2) #define RST_DPLL3 BIT2
#define GLOBAL_SW_RST (0x1UL << 1) #define GLOBAL_SW_RST BIT1
#define GLOBAL_COLD_RST (0x0UL << 0) #define GLOBAL_COLD_RST (0x0UL << 0)
#endif // __OMAP3530PRCM_H__ #endif // __OMAP3530PRCM_H__

22
Omap35xxPkg/Include/Omap3530/Omap3530Timer.h
View File

@ -51,9 +51,9 @@
#define WSPR (0x048) #define WSPR (0x048)
#define TISR_TCAR_IT_FLAG_MASK (1UL << 2) #define TISR_TCAR_IT_FLAG_MASK BIT2
#define TISR_OVF_IT_FLAG_MASK (1UL << 1) #define TISR_OVF_IT_FLAG_MASK BIT1
#define TISR_MAT_IT_FLAG_MASK (1UL << 0) #define TISR_MAT_IT_FLAG_MASK BIT0
#define TISR_ALL_INTERRUPT_MASK (TISR_TCAR_IT_FLAG_MASK | TISR_OVF_IT_FLAG_MASK | TISR_MAT_IT_FLAG_MASK) #define TISR_ALL_INTERRUPT_MASK (TISR_TCAR_IT_FLAG_MASK | TISR_OVF_IT_FLAG_MASK | TISR_MAT_IT_FLAG_MASK)
#define TISR_TCAR_IT_FLAG_NOT_PENDING (0UL << 2) #define TISR_TCAR_IT_FLAG_NOT_PENDING (0UL << 2)
@ -61,21 +61,21 @@
#define TISR_MAT_IT_FLAG_NOT_PENDING (0UL << 0) #define TISR_MAT_IT_FLAG_NOT_PENDING (0UL << 0)
#define TISR_NO_INTERRUPTS_PENDING (TISR_TCAR_IT_FLAG_NOT_PENDING | TISR_OVF_IT_FLAG_NOT_PENDING | TISR_MAT_IT_FLAG_NOT_PENDING) #define TISR_NO_INTERRUPTS_PENDING (TISR_TCAR_IT_FLAG_NOT_PENDING | TISR_OVF_IT_FLAG_NOT_PENDING | TISR_MAT_IT_FLAG_NOT_PENDING)
#define TISR_TCAR_IT_FLAG_CLEAR (1UL << 2) #define TISR_TCAR_IT_FLAG_CLEAR BIT2
#define TISR_OVF_IT_FLAG_CLEAR (1UL << 1) #define TISR_OVF_IT_FLAG_CLEAR BIT1
#define TISR_MAT_IT_FLAG_CLEAR (1UL << 0) #define TISR_MAT_IT_FLAG_CLEAR BIT0
#define TISR_CLEAR_ALL (TISR_TCAR_IT_FLAG_CLEAR | TISR_OVF_IT_FLAG_CLEAR | TISR_MAT_IT_FLAG_CLEAR) #define TISR_CLEAR_ALL (TISR_TCAR_IT_FLAG_CLEAR | TISR_OVF_IT_FLAG_CLEAR | TISR_MAT_IT_FLAG_CLEAR)
#define TCLR_AR_AUTORELOAD (1UL << 1) #define TCLR_AR_AUTORELOAD BIT1
#define TCLR_AR_ONESHOT (0UL << 1) #define TCLR_AR_ONESHOT (0UL << 1)
#define TCLR_ST_ON (1UL << 0) #define TCLR_ST_ON BIT0
#define TCLR_ST_OFF (0UL << 0) #define TCLR_ST_OFF (0UL << 0)
#define TIER_TCAR_IT_ENABLE (1UL << 2) #define TIER_TCAR_IT_ENABLE (BIT2
#define TIER_TCAR_IT_DISABLE (0UL << 2) #define TIER_TCAR_IT_DISABLE (0UL << 2)
#define TIER_OVF_IT_ENABLE (1UL << 1) #define TIER_OVF_IT_ENABLE BIT1
#define TIER_OVF_IT_DISABLE (0UL << 1) #define TIER_OVF_IT_DISABLE (0UL << 1)
#define TIER_MAT_IT_ENABLE (1UL << 0) #define TIER_MAT_IT_ENABLE BIT0
#define TIER_MAT_IT_DISABLE (0UL << 0) #define TIER_MAT_IT_DISABLE (0UL << 0)
#endif // __OMAP3530TIMER_H__ #endif // __OMAP3530TIMER_H__

27
Omap35xxPkg/Include/Omap3530/Omap3530Uart.h
View File

@ -29,25 +29,26 @@
#define UART_LSR_REG (0x0014) #define UART_LSR_REG (0x0014)
#define UART_MDR1_REG (0x0020) #define UART_MDR1_REG (0x0020)
#define UART_FCR_TX_FIFO_CLEAR (1UL << 3) #define UART_FCR_TX_FIFO_CLEAR BIT2
#define UART_FCR_RX_FIFO_CLEAR (1UL << 3) #define UART_FCR_RX_FIFO_CLEAR BIT1
#define UART_FCR_FIFO_ENABLE (1UL << 3) #define UART_FCR_FIFO_ENABLE BIT0
#define UART_LCR_DIV_EN_ENABLE (1UL << 7) #define UART_LCR_DIV_EN_ENABLE BIT7
#define UART_LCR_DIV_EN_DISABLE (0UL << 7) #define UART_LCR_DIV_EN_DISABLE (0UL << 7)
#define UART_LCR_CHAR_LENGTH_8 (3UL << 0) #define UART_LCR_CHAR_LENGTH_8 (BIT1 | BIT0)
#define UART_MCR_RTS_FORCE_ACTIVE (1UL << 1) #define UART_MCR_RTS_FORCE_ACTIVE BIT1
#define UART_MCR_DTR_FORCE_ACTIVE (1UL << 0) #define UART_MCR_DTR_FORCE_ACTIVE BIT0
#define UART_LSR_TX_FIFO_E_MASK (1UL << 5) #define UART_LSR_TX_FIFO_E_MASK BIT5
#define UART_LSR_TX_FIFO_E_NOT_EMPTY (0UL << 5) #define UART_LSR_TX_FIFO_E_NOT_EMPTY (0UL << 5)
#define UART_LSR_TX_FIFO_E_EMPTY (1UL << 5) #define UART_LSR_TX_FIFO_E_EMPTY BIT5
#define UART_LSR_RX_FIFO_E_MASK (1UL << 0) #define UART_LSR_RX_FIFO_E_MASK BIT0
#define UART_LSR_RX_FIFO_E_NOT_EMPTY (1UL << 0) #define UART_LSR_RX_FIFO_E_NOT_EMPTY BIT0
#define UART_LSR_RX_FIFO_E_EMPTY (0UL << 0) #define UART_LSR_RX_FIFO_E_EMPTY (0UL << 0)
#define UART_MDR1_MODE_SELECT_DISABLE (7UL << 0) // BIT2:BIT0
#define UART_MDR1_MODE_SELECT_UART_16X (0UL << 0) #define UART_MDR1_MODE_SELECT_DISABLE (7UL)
#define UART_MDR1_MODE_SELECT_UART_16X (0UL)
#endif // __OMAP3530UART_H__ #endif // __OMAP3530UART_H__

23
Omap35xxPkg/Include/Omap3530/Omap3530Usb.h
View File

@ -23,20 +23,25 @@
#define USB_EHCI_HCCAPBASE (USB_BASE + 0x4800) #define USB_EHCI_HCCAPBASE (USB_BASE + 0x4800)
#define UHH_SYSCONFIG_MIDLEMODE_NO_STANDBY (1UL << 12) #define UHH_SYSCONFIG_MIDLEMODE_NO_STANDBY BIT12
#define UHH_SYSCONFIG_CLOCKACTIVITY_ON (1UL << 8) #define UHH_SYSCONFIG_CLOCKACTIVITY_ON BIT8
#define UHH_SYSCONFIG_SIDLEMODE_NO_STANDBY (1UL << 3) #define UHH_SYSCONFIG_SIDLEMODE_NO_STANDBY BIT3
#define UHH_SYSCONFIG_ENAWAKEUP_ENABLE (1UL << 2) #define UHH_SYSCONFIG_ENAWAKEUP_ENABLE BIT2
#define UHH_SYSCONFIG_SOFTRESET (1UL << 1) #define UHH_SYSCONFIG_SOFTRESET BIT1
#define UHH_SYSCONFIG_AUTOIDLE_ALWAYS_RUN (0UL << 0) #define UHH_SYSCONFIG_AUTOIDLE_ALWAYS_RUN (0UL << 0)
#define UHH_HOSTCONFIG_ENA_INCR16_ENABLE (1UL << 4) #define UHH_HOSTCONFIG_P3_CONNECT_STATUS_DISCONNECT (0UL << 10)
#define UHH_HOSTCONFIG_ENA_INCR8_ENABLE (1UL << 3) #define UHH_HOSTCONFIG_P2_CONNECT_STATUS_DISCONNECT (0UL << 9)
#define UHH_HOSTCONFIG_ENA_INCR4_ENABLE (1UL << 2) #define UHH_HOSTCONFIG_P1_CONNECT_STATUS_DISCONNECT (0UL << 8)
#define UHH_HOSTCONFIG_ENA_INCR_ALIGN_DISABLE (0UL << 5)
#define UHH_HOSTCONFIG_ENA_INCR16_ENABLE BIT4
#define UHH_HOSTCONFIG_ENA_INCR8_ENABLE BIT3
#define UHH_HOSTCONFIG_ENA_INCR4_ENABLE BIT2
#define UHH_HOSTCONFIG_AUTOPPD_ON_OVERCUR_EN_ON (0UL << 1)
#define UHH_HOSTCONFIG_P1_ULPI_BYPASS_ULPI_MODE (0UL << 0)
#define UHH_SYSSTATUS_RESETDONE (BIT0 | BIT1 | BIT2) #define UHH_SYSSTATUS_RESETDONE (BIT0 | BIT1 | BIT2)
#endif // __OMAP3530USB_H__ #endif // __OMAP3530USB_H__

10
Omap35xxPkg/Include/TPS65950.h
View File

@ -28,7 +28,7 @@
//MMC definitions. //MMC definitions.
#define VMMC1_DEV_GRP 0x82 #define VMMC1_DEV_GRP 0x82
#define DEV_GRP_P1 (0x01UL << 5) #define DEV_GRP_P1 BIT5
#define VMMC1_DEDICATED_REG 0x85 #define VMMC1_DEDICATED_REG 0x85
#define VSEL_1_85V 0x0 #define VSEL_1_85V 0x0
@ -38,9 +38,9 @@
//LEDEN register //LEDEN register
#define LEDEN 0xEE #define LEDEN 0xEE
#define LEDAON (0x1UL << 0) #define LEDAON BIT0
#define LEDBON (0x1UL << 1) #define LEDBON BIT1
#define LEDAPWM (0x1UL << 4) #define LEDAPWM BIT4
#define LEDBPWM (0x1UL << 5) #define LEDBPWM BIT5
#endif //__TPS65950_H__ #endif //__TPS65950_H__

4
Omap35xxPkg/InterruptDxe/HardwareInterrupt.c
View File

@ -59,6 +59,8 @@ ExitBootServicesEvent (
MmioWrite32 (INTCPS_MIR(1), 0xFFFFFFFF); MmioWrite32 (INTCPS_MIR(1), 0xFFFFFFFF);
MmioWrite32 (INTCPS_MIR(2), 0xFFFFFFFF); MmioWrite32 (INTCPS_MIR(2), 0xFFFFFFFF);
MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR); MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);
// Add code here to disable all FIQs as debugger may have turned one on
} }
/** /**
@ -201,7 +203,7 @@ GetInterruptSourceState (
Bank = Source / 32; Bank = Source / 32;
Bit = 1UL << (Source % 32); Bit = 1UL << (Source % 32);
if ((MmioRead32(INTCPS_MIR(Bank)) & Bit) == Bit) { if ((MmioRead32 (INTCPS_MIR(Bank)) & Bit) == Bit) {
*InterruptState = FALSE; *InterruptState = FALSE;
} else { } else {
*InterruptState = TRUE; *InterruptState = TRUE;

4
Omap35xxPkg/Library/BeagleBoardSystemLib/BeagleBoardSystemLib.c
View File

@ -39,8 +39,8 @@ ResetSystem (
case EfiResetShutdown: case EfiResetShutdown:
default: default:
//Perform cold reset of the system. //Perform cold reset of the system.
MmioOr32(PRM_RSTCTRL, RST_DPLL3); MmioOr32 (PRM_RSTCTRL, RST_DPLL3);
while ((MmioRead32(PRM_RSTST) & GLOBAL_COLD_RST) != 0x1); while ((MmioRead32 (PRM_RSTST) & GLOBAL_COLD_RST) != 0x1);
break; break;
} }

2
Omap35xxPkg/Library/BeagleBoardTimerLib/BeagleBoardTimerLib.inf
View File

@ -41,5 +41,5 @@
[Pcd] [Pcd]
gEmbeddedTokenSpaceGuid.PcdEmbeddedPerformanceCounterFreqencyInHz gEmbeddedTokenSpaceGuid.PcdEmbeddedPerformanceCounterFreqencyInHz
gEmbeddedTokenSpaceGuid.PcdEmbeddedFdPerformanceCounterPeriodInNanoseconds gEmbeddedTokenSpaceGuid.PcdEmbeddedFdPerformanceCounterPeriodInNanoseconds
gOmap35xxTokenSpaceGuid.PcdBeagleFreeTimer gOmap35xxTokenSpaceGuid.PcdOmap35xxFreeTimer

10
Omap35xxPkg/Library/BeagleBoardTimerLib/TimerLib.c
View File

@ -57,13 +57,13 @@ NanoSecondDelay (
Delay = (NanoSeconds / PcdGet32(PcdEmbeddedFdPerformanceCounterPeriodInNanoseconds)) + 1; Delay = (NanoSeconds / PcdGet32(PcdEmbeddedFdPerformanceCounterPeriodInNanoseconds)) + 1;
TimerCountRegister = TimerBase(PcdGet32(PcdBeagleFreeTimer)) + GPTIMER_TCRR; TimerCountRegister = TimerBase(PcdGet32(PcdOmap35xxFreeTimer)) + GPTIMER_TCRR;
StartTime = MmioRead32(TimerCountRegister); StartTime = MmioRead32 (TimerCountRegister);
do do
{ {
CurrentTime = MmioRead32(TimerCountRegister); CurrentTime = MmioRead32 (TimerCountRegister);
ElapsedTime = CurrentTime - StartTime; ElapsedTime = CurrentTime - StartTime;
} while (ElapsedTime < Delay); } while (ElapsedTime < Delay);
@ -78,7 +78,7 @@ GetPerformanceCounter (
VOID VOID
) )
{ {
return (UINT64)MmioRead32(TimerBase(PcdGet32(PcdBeagleFreeTimer)) + GPTIMER_TCRR); return (UINT64)MmioRead32 (TimerBase(PcdGet32(PcdOmap35xxFreeTimer)) + GPTIMER_TCRR);
} }
UINT64 UINT64
@ -90,7 +90,7 @@ GetPerformanceCounterProperties (
{ {
if (StartValue != NULL) { if (StartValue != NULL) {
// Timer starts with the reload value // Timer starts with the reload value
*StartValue = (UINT64)MmioRead32(TimerBase(PcdGet32(PcdBeagleFreeTimer)) + GPTIMER_TLDR); *StartValue = (UINT64)MmioRead32 (TimerBase(PcdGet32(PcdOmap35xxFreeTimer)) + GPTIMER_TLDR);
} }
if (EndValue != NULL) { if (EndValue != NULL) {

158
Omap35xxPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.c Executable file
View File

@ -0,0 +1,158 @@
/** @file
Debug Agent timer lib for OMAP 35xx.
Copyright (c) 2008-2010, Apple Inc. All rights reserved.
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <Base.h>
#include <Library/BaseLib.h>
#include <Library/IoLib.h>
#include <Library/OmapLib.h>
#include <Library/ArmLib.h>
#include <Library/PcdLib.h>
#include <Omap3530/Omap3530.h>
volatile UINT32 gVector;
// Cached registers
volatile UINT32 gTISR;
volatile UINT32 gTCLR;
volatile UINT32 gTLDR;
volatile UINT32 gTCRR;
volatile UINT32 gTIER;
VOID
EnableInterruptSource (
VOID
)
{
UINTN Bank;
UINTN Bit;
// Map vector to FIQ, IRQ is default
MmioWrite32 (INTCPS_ILR (gVector), 1);
Bank = gVector / 32;
Bit = 1UL << (gVector % 32);
MmioWrite32 (INTCPS_MIR_CLEAR(Bank), Bit);
}
VOID
DisableInterruptSource (
VOID
)
{
UINTN Bank;
UINTN Bit;
Bank = gVector / 32;
Bit = 1UL << (gVector % 32);
MmioWrite32 (INTCPS_MIR_SET(Bank), Bit);
}
/**
Setup all the hardware needed for the debug agents timer.
This function is used to set up debug enviroment. It may enable interrupts.
**/
VOID
EFIAPI
DebugAgentTimerIntialize (
VOID
)
{
UINT32 TimerBaseAddress;
gVector = InterruptVectorForTimer (PcdGet32(PcdOmap35xxDebugAgentTimer));
// Set up the timer registers
TimerBaseAddress = TimerBase (PcdGet32(PcdOmap35xxDebugAgentTimer));
gTISR = TimerBaseAddress + GPTIMER_TISR;
gTCLR = TimerBaseAddress + GPTIMER_TCLR;
gTLDR = TimerBaseAddress + GPTIMER_TLDR;
gTCRR = TimerBaseAddress + GPTIMER_TCRR;
gTIER = TimerBaseAddress + GPTIMER_TIER;
DisableInterruptSource ();
}
/**
Set the period for the debug agent timer. Zero means disable the timer.
@param[in] TimerPeriodMilliseconds Frequency of the debug agent timer.
**/
VOID
EFIAPI
DebugAgentTimerSetPeriod (
IN UINT32 TimerPeriodMilliseconds
)
{
UINT64 TimerCount;
INT32 LoadValue;
if (TimerPeriodMilliseconds == 0) {
// Turn off GPTIMER3
MmioWrite32 (gTCLR, TCLR_ST_OFF);
DisableInterruptSource ();
} else {
// Calculate required timer count
TimerCount = DivU64x32(TimerPeriodMilliseconds * 1000000, PcdGet32(PcdDebugAgentTimerFreqNanoSeconds));
// Set GPTIMER5 Load register
LoadValue = (INT32) -TimerCount;
MmioWrite32 (gTLDR, LoadValue);
MmioWrite32 (gTCRR, LoadValue);
// Enable Overflow interrupt
MmioWrite32 (gTIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_ENABLE | TIER_MAT_IT_DISABLE);
// Turn on GPTIMER3, it will reload at overflow
MmioWrite32 (gTCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON);
EnableInterruptSource ();
}
}
/**
Perform End Of Interrupt for the debug agent timer. This is called in the
interrupt handler after the interrupt has been processed.
**/
VOID
EFIAPI
DebugAgentTimerEndOfInterrupt (
VOID
)
{
// Clear all timer interrupts
MmioWrite32 (gTISR, TISR_CLEAR_ALL);
// Poll interrupt status bits to ensure clearing
while ((MmioRead32 (gTISR) & TISR_ALL_INTERRUPT_MASK) != TISR_NO_INTERRUPTS_PENDING);
MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWFIQAGR);
ArmDataSyncronizationBarrier ();
}

47
Omap35xxPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.inf Executable file
View File

@ -0,0 +1,47 @@
#/** @file
# Component description file for Base PCI Cf8 Library.
#
# PCI CF8 Library that uses I/O ports 0xCF8 and 0xCFC to perform PCI Configuration cycles.
# Layers on top of an I/O Library instance.
# Copyright (c) 2007, Intel Corporation.
#
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = DebugAgentTimerLibNull
FILE_GUID = E82F99DE-74ED-4e56-BBA1-B143FCA3F69A
MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = DebugAgentTimerLib|SEC BASE DXE_CORE
[Sources.common]
DebugAgentTimerLib.c
[Packages]
MdePkg/MdePkg.dec
EmbeddedPkg/EmbeddedPkg.dec
Omap35xxPkg/Omap35xxPkg.dec
ArmPkg/ArmPkg.dec
[LibraryClasses]
BaseLib
IoLib
OmapLib
ArmLib
[Pcd]
gOmap35xxTokenSpaceGuid.PcdOmap35xxDebugAgentTimer
gOmap35xxTokenSpaceGuid.PcdDebugAgentTimerFreqNanoSeconds

13
Omap35xxPkg/Library/GdbSerialLib/GdbSerialLib.c
View File

@ -24,8 +24,7 @@
RETURN_STATUS RETURN_STATUS
EFIAPI EFIAPI
GdbSerialLibConstructor ( GdbSerialLibConstructor (
IN EFI_HANDLE ImageHandle, VOID
IN EFI_SYSTEM_TABLE *SystemTable
) )
{ {
return RETURN_SUCCESS; return RETURN_SUCCESS;
@ -49,7 +48,7 @@ GdbIsCharAvailable (
VOID VOID
) )
{ {
UINT32 LSR = UartBase(PcdGet32(PcdBeagleConsoleUart)) + UART_LSR_REG; UINT32 LSR = UartBase(PcdGet32(PcdOmap35xxConsoleUart)) + UART_LSR_REG;
if ((MmioRead8(LSR) & UART_LSR_RX_FIFO_E_MASK) == UART_LSR_RX_FIFO_E_NOT_EMPTY) { if ((MmioRead8(LSR) & UART_LSR_RX_FIFO_E_MASK) == UART_LSR_RX_FIFO_E_NOT_EMPTY) {
return TRUE; return TRUE;
@ -64,8 +63,8 @@ GdbGetChar (
VOID VOID
) )
{ {
UINT32 LSR = UartBase(PcdGet32(PcdBeagleConsoleUart)) + UART_LSR_REG; UINT32 LSR = UartBase(PcdGet32(PcdOmap35xxConsoleUart)) + UART_LSR_REG;
UINT32 RBR = UartBase(PcdGet32(PcdBeagleConsoleUart)) + UART_RBR_REG; UINT32 RBR = UartBase(PcdGet32(PcdOmap35xxConsoleUart)) + UART_RBR_REG;
CHAR8 Char; CHAR8 Char;
while ((MmioRead8(LSR) & UART_LSR_RX_FIFO_E_MASK) == UART_LSR_RX_FIFO_E_EMPTY); while ((MmioRead8(LSR) & UART_LSR_RX_FIFO_E_MASK) == UART_LSR_RX_FIFO_E_EMPTY);
@ -80,8 +79,8 @@ GdbPutChar (
IN CHAR8 Char IN CHAR8 Char
) )
{ {
UINT32 LSR = UartBase(PcdGet32(PcdBeagleConsoleUart)) + UART_LSR_REG; UINT32 LSR = UartBase(PcdGet32(PcdOmap35xxConsoleUart)) + UART_LSR_REG;
UINT32 THR = UartBase(PcdGet32(PcdBeagleConsoleUart)) + UART_THR_REG; UINT32 THR = UartBase(PcdGet32(PcdOmap35xxConsoleUart)) + UART_THR_REG;
while ((MmioRead8(LSR) & UART_LSR_TX_FIFO_E_MASK) == UART_LSR_TX_FIFO_E_NOT_EMPTY); while ((MmioRead8(LSR) & UART_LSR_TX_FIFO_E_MASK) == UART_LSR_TX_FIFO_E_NOT_EMPTY);
MmioWrite8(THR, Char); MmioWrite8(THR, Char);

4
Omap35xxPkg/Library/GdbSerialLib/GdbSerialLib.inf
View File

@ -15,7 +15,7 @@
INF_VERSION = 0x00010005 INF_VERSION = 0x00010005
BASE_NAME = GdbSerialLib BASE_NAME = GdbSerialLib
FILE_GUID = E2423349-EF5D-439B-95F5-8B8D8E3B443F FILE_GUID = E2423349-EF5D-439B-95F5-8B8D8E3B443F
MODULE_TYPE = UEFI_DRIVER MODULE_TYPE = BASE
VERSION_STRING = 1.0 VERSION_STRING = 1.0
LIBRARY_CLASS = GdbSerialLib LIBRARY_CLASS = GdbSerialLib
@ -37,5 +37,5 @@
OmapLib OmapLib
[FixedPcd] [FixedPcd]
gOmap35xxTokenSpaceGuid.PcdBeagleConsoleUart gOmap35xxTokenSpaceGuid.PcdOmap35xxConsoleUart

2
Omap35xxPkg/Library/ResetSystemLib/ResetSystemLib.c
View File

@ -59,7 +59,7 @@ LibResetSystem (
default: default:
// Perform cold reset of the system. // Perform cold reset of the system.
MmioOr32 (PRM_RSTCTRL, RST_DPLL3); MmioOr32 (PRM_RSTCTRL, RST_DPLL3);
while ((MmioRead32(PRM_RSTST) & GLOBAL_COLD_RST) != 0x1); while ((MmioRead32 (PRM_RSTST) & GLOBAL_COLD_RST) != 0x1);
break; break;
} }

10
Omap35xxPkg/Library/SerialPortLib/SerialPortLib.c
View File

@ -56,8 +56,8 @@ SerialPortWrite (
IN UINTN NumberOfBytes IN UINTN NumberOfBytes
) )
{ {
UINT32 LSR = UartBase(PcdGet32(PcdBeagleConsoleUart)) + UART_LSR_REG; UINT32 LSR = UartBase(PcdGet32(PcdOmap35xxConsoleUart)) + UART_LSR_REG;
UINT32 THR = UartBase(PcdGet32(PcdBeagleConsoleUart)) + UART_THR_REG; UINT32 THR = UartBase(PcdGet32(PcdOmap35xxConsoleUart)) + UART_THR_REG;
UINTN Count; UINTN Count;
for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) { for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) {
@ -86,8 +86,8 @@ SerialPortRead (
IN UINTN NumberOfBytes IN UINTN NumberOfBytes
) )
{ {
UINT32 LSR = UartBase(PcdGet32(PcdBeagleConsoleUart)) + UART_LSR_REG; UINT32 LSR = UartBase(PcdGet32(PcdOmap35xxConsoleUart)) + UART_LSR_REG;
UINT32 RBR = UartBase(PcdGet32(PcdBeagleConsoleUart)) + UART_RBR_REG; UINT32 RBR = UartBase(PcdGet32(PcdOmap35xxConsoleUart)) + UART_RBR_REG;
UINTN Count; UINTN Count;
for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) { for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) {
@ -113,7 +113,7 @@ SerialPortPoll (
VOID VOID
) )
{ {
UINT32 LSR = UartBase(PcdGet32(PcdBeagleConsoleUart)) + UART_LSR_REG; UINT32 LSR = UartBase(PcdGet32(PcdOmap35xxConsoleUart)) + UART_LSR_REG;
if ((MmioRead8(LSR) & UART_LSR_RX_FIFO_E_MASK) == UART_LSR_RX_FIFO_E_NOT_EMPTY) { if ((MmioRead8(LSR) & UART_LSR_RX_FIFO_E_MASK) == UART_LSR_RX_FIFO_E_NOT_EMPTY) {
return TRUE; return TRUE;

2
Omap35xxPkg/Library/SerialPortLib/SerialPortLib.inf
View File

@ -39,5 +39,5 @@
Omap35xxPkg/Omap35xxPkg.dec Omap35xxPkg/Omap35xxPkg.dec
[FixedPcd] [FixedPcd]
gOmap35xxTokenSpaceGuid.PcdBeagleConsoleUart gOmap35xxTokenSpaceGuid.PcdOmap35xxConsoleUart

100
Omap35xxPkg/MMCHSDxe/MMCHS.c
View File

@ -92,10 +92,10 @@ UpdateMMCHSClkFrequency (
MmioAndThenOr32(MMCHS_SYSCTL, ~CLKD_MASK, NewCLKD << 6); MmioAndThenOr32(MMCHS_SYSCTL, ~CLKD_MASK, NewCLKD << 6);
//Poll till Internal Clock Stable //Poll till Internal Clock Stable
while ((MmioRead32(MMCHS_SYSCTL) & ICS_MASK) != ICS); while ((MmioRead32 (MMCHS_SYSCTL) & ICS_MASK) != ICS);
//Set Clock enable to 0x1 to provide the clock to the card //Set Clock enable to 0x1 to provide the clock to the card
MmioOr32(MMCHS_SYSCTL, CEN); MmioOr32 (MMCHS_SYSCTL, CEN);
} }
STATIC STATIC
@ -110,7 +110,7 @@ SendCmd (
UINTN RetryCount = 0; UINTN RetryCount = 0;
//Check if command line is in use or not. Poll till command line is available. //Check if command line is in use or not. Poll till command line is available.
while ((MmioRead32(MMCHS_PSTATE) & DATI_MASK) == DATI_NOT_ALLOWED); while ((MmioRead32 (MMCHS_PSTATE) & DATI_MASK) == DATI_NOT_ALLOWED);
//Provide the block size. //Provide the block size.
MmioWrite32 (MMCHS_BLK, BLEN_512BYTES); MmioWrite32 (MMCHS_BLK, BLEN_512BYTES);
@ -133,15 +133,15 @@ SendCmd (
//Check for the command status. //Check for the command status.
while (RetryCount < MAX_RETRY_COUNT) { while (RetryCount < MAX_RETRY_COUNT) {
do { do {
MmcStatus = MmioRead32(MMCHS_STAT); MmcStatus = MmioRead32 (MMCHS_STAT);
} while (MmcStatus == 0); } while (MmcStatus == 0);
//Read status of command response //Read status of command response
if ((MmcStatus & ERRI) != 0) { if ((MmcStatus & ERRI) != 0) {
//Perform soft-reset for mmci_cmd line. //Perform soft-reset for mmci_cmd line.
MmioOr32(MMCHS_SYSCTL, SRC); MmioOr32 (MMCHS_SYSCTL, SRC);
while ((MmioRead32(MMCHS_SYSCTL) & SRC)); while ((MmioRead32 (MMCHS_SYSCTL) & SRC));
DEBUG ((EFI_D_INFO, "MmcStatus: %x\n", MmcStatus)); DEBUG ((EFI_D_INFO, "MmcStatus: %x\n", MmcStatus));
return EFI_DEVICE_ERROR; return EFI_DEVICE_ERROR;
@ -351,41 +351,41 @@ InitializeMMCHS (
ASSERT_EFI_ERROR(Status); ASSERT_EFI_ERROR(Status);
//After ramping up voltage, set VDDS stable bit to indicate that voltage level is stable. //After ramping up voltage, set VDDS stable bit to indicate that voltage level is stable.
MmioOr32(CONTROL_PBIAS_LITE, (PBIASLITEVMODE0 | PBIASLITEPWRDNZ0 | PBIASSPEEDCTRL0 | PBIASLITEVMODE1 | PBIASLITEWRDNZ1)); MmioOr32 (CONTROL_PBIAS_LITE, (PBIASLITEVMODE0 | PBIASLITEPWRDNZ0 | PBIASSPEEDCTRL0 | PBIASLITEVMODE1 | PBIASLITEWRDNZ1));
//Software reset of the MMCHS host controller. //Software reset of the MMCHS host controller.
MmioWrite32 (MMCHS_SYSCONFIG, SOFTRESET); MmioWrite32 (MMCHS_SYSCONFIG, SOFTRESET);
gBS->Stall(1000); gBS->Stall(1000);
while ((MmioRead32(MMCHS_SYSSTATUS) & RESETDONE_MASK) != RESETDONE); while ((MmioRead32 (MMCHS_SYSSTATUS) & RESETDONE_MASK) != RESETDONE);
//Soft reset for all. //Soft reset for all.
MmioWrite32 (MMCHS_SYSCTL, SRA); MmioWrite32 (MMCHS_SYSCTL, SRA);
gBS->Stall(1000); gBS->Stall(1000);
while ((MmioRead32(MMCHS_SYSCTL) & SRA) != 0x0); while ((MmioRead32 (MMCHS_SYSCTL) & SRA) != 0x0);
//Voltage capabilities initialization. Activate VS18 and VS30. //Voltage capabilities initialization. Activate VS18 and VS30.
MmioOr32(MMCHS_CAPA, (VS30 | VS18)); MmioOr32 (MMCHS_CAPA, (VS30 | VS18));
//Wakeup configuration //Wakeup configuration
MmioOr32(MMCHS_SYSCONFIG, ENAWAKEUP); MmioOr32 (MMCHS_SYSCONFIG, ENAWAKEUP);
MmioOr32(MMCHS_HCTL, IWE); MmioOr32 (MMCHS_HCTL, IWE);
//MMCHS Controller default initialization //MMCHS Controller default initialization
MmioOr32(MMCHS_CON, (OD | DW8_1_4_BIT | CEATA_OFF)); MmioOr32 (MMCHS_CON, (OD | DW8_1_4_BIT | CEATA_OFF));
MmioWrite32 (MMCHS_HCTL, (SDVS_3_0_V | DTW_1_BIT | SDBP_OFF)); MmioWrite32 (MMCHS_HCTL, (SDVS_3_0_V | DTW_1_BIT | SDBP_OFF));
//Enable internal clock //Enable internal clock
MmioOr32(MMCHS_SYSCTL, ICE); MmioOr32 (MMCHS_SYSCTL, ICE);
//Set the clock frequency to 80KHz. //Set the clock frequency to 80KHz.
UpdateMMCHSClkFrequency(CLKD_80KHZ); UpdateMMCHSClkFrequency(CLKD_80KHZ);
//Enable SD bus power. //Enable SD bus power.
MmioOr32(MMCHS_HCTL, (SDBP_ON)); MmioOr32 (MMCHS_HCTL, (SDBP_ON));
//Poll till SD bus power bit is set. //Poll till SD bus power bit is set.
while ((MmioRead32(MMCHS_HCTL) & SDBP_MASK) != SDBP_ON); while ((MmioRead32 (MMCHS_HCTL) & SDBP_MASK) != SDBP_ON);
return Status; return Status;
} }
@ -407,29 +407,29 @@ PerformCardIdenfication (
CEB_EN | CCRC_EN | CTO_EN | BRR_EN | BWR_EN | TC_EN | CC_EN)); CEB_EN | CCRC_EN | CTO_EN | BRR_EN | BWR_EN | TC_EN | CC_EN));
//Controller INIT procedure start. //Controller INIT procedure start.
MmioOr32(MMCHS_CON, INIT); MmioOr32 (MMCHS_CON, INIT);
MmioWrite32 (MMCHS_CMD, 0x00000000); MmioWrite32 (MMCHS_CMD, 0x00000000);
while (!(MmioRead32(MMCHS_STAT) & CC)); while (!(MmioRead32 (MMCHS_STAT) & CC));
//Wait for 1 ms //Wait for 1 ms
gBS->Stall(1000); gBS->Stall(1000);
//Set CC bit to 0x1 to clear the flag //Set CC bit to 0x1 to clear the flag
MmioOr32(MMCHS_STAT, CC); MmioOr32 (MMCHS_STAT, CC);
//Retry INIT procedure. //Retry INIT procedure.
MmioWrite32 (MMCHS_CMD, 0x00000000); MmioWrite32 (MMCHS_CMD, 0x00000000);
while (!(MmioRead32(MMCHS_STAT) & CC)); while (!(MmioRead32 (MMCHS_STAT) & CC));
//End initialization sequence //End initialization sequence
MmioAnd32(MMCHS_CON, ~INIT); MmioAnd32(MMCHS_CON, ~INIT);
MmioOr32(MMCHS_HCTL, (SDVS_3_0_V | DTW_1_BIT | SDBP_ON)); MmioOr32 (MMCHS_HCTL, (SDVS_3_0_V | DTW_1_BIT | SDBP_ON));
//Change clock frequency to 400KHz to fit protocol //Change clock frequency to 400KHz to fit protocol
UpdateMMCHSClkFrequency(CLKD_400KHZ); UpdateMMCHSClkFrequency(CLKD_400KHZ);
MmioOr32(MMCHS_CON, OD); MmioOr32 (MMCHS_CON, OD);
//Send CMD0 command. //Send CMD0 command.
Status = SendCmd(CMD0, CMD0_INT_EN, CmdArgument); Status = SendCmd(CMD0, CMD0_INT_EN, CmdArgument);
@ -438,22 +438,22 @@ PerformCardIdenfication (
return Status; return Status;
} }
DEBUG ((EFI_D_INFO, "CMD0 response: %x\n", MmioRead32(MMCHS_RSP10))); DEBUG ((EFI_D_INFO, "CMD0 response: %x\n", MmioRead32 (MMCHS_RSP10)));
//Send CMD5 command. //Send CMD5 command.
Status = SendCmd(CMD5, CMD5_INT_EN, CmdArgument); Status = SendCmd(CMD5, CMD5_INT_EN, CmdArgument);
if (Status == EFI_SUCCESS) { if (Status == EFI_SUCCESS) {
DEBUG ((EFI_D_ERROR, "CMD5 Success. SDIO card. Follow SDIO card specification.\n")); DEBUG ((EFI_D_ERROR, "CMD5 Success. SDIO card. Follow SDIO card specification.\n"));
DEBUG ((EFI_D_INFO, "CMD5 response: %x\n", MmioRead32(MMCHS_RSP10))); DEBUG ((EFI_D_INFO, "CMD5 response: %x\n", MmioRead32 (MMCHS_RSP10)));
//NOTE: Returning unsupported error for now. Need to implement SDIO specification. //NOTE: Returning unsupported error for now. Need to implement SDIO specification.
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} else { } else {
DEBUG ((EFI_D_INFO, "CMD5 fails. Not an SDIO card.\n")); DEBUG ((EFI_D_INFO, "CMD5 fails. Not an SDIO card.\n"));
} }
MmioOr32(MMCHS_SYSCTL, SRC); MmioOr32 (MMCHS_SYSCTL, SRC);
gBS->Stall(1000); gBS->Stall(1000);
while ((MmioRead32(MMCHS_SYSCTL) & SRC)); while ((MmioRead32 (MMCHS_SYSCTL) & SRC));
//Send CMD8 command. (New v2.00 command for Voltage check) //Send CMD8 command. (New v2.00 command for Voltage check)
//Only 2.7V - 3.6V is supported for SD2.0, only SD 2.0 card can pass. //Only 2.7V - 3.6V is supported for SD2.0, only SD 2.0 card can pass.
@ -461,7 +461,7 @@ PerformCardIdenfication (
CmdArgument = CMD8_ARG; CmdArgument = CMD8_ARG;
Status = SendCmd(CMD8, CMD8_INT_EN, CmdArgument); Status = SendCmd(CMD8, CMD8_INT_EN, CmdArgument);
if (Status == EFI_SUCCESS) { if (Status == EFI_SUCCESS) {
Response = MmioRead32(MMCHS_RSP10); Response = MmioRead32 (MMCHS_RSP10);
DEBUG ((EFI_D_INFO, "CMD8 success. CMD8 response: %x\n", Response)); DEBUG ((EFI_D_INFO, "CMD8 success. CMD8 response: %x\n", Response));
if (Response != CmdArgument) { if (Response != CmdArgument) {
return EFI_DEVICE_ERROR; return EFI_DEVICE_ERROR;
@ -472,9 +472,9 @@ PerformCardIdenfication (
DEBUG ((EFI_D_INFO, "CMD8 fails. Not an SD2.0 card.\n")); DEBUG ((EFI_D_INFO, "CMD8 fails. Not an SD2.0 card.\n"));
} }
MmioOr32(MMCHS_SYSCTL, SRC); MmioOr32 (MMCHS_SYSCTL, SRC);
gBS->Stall(1000); gBS->Stall(1000);
while ((MmioRead32(MMCHS_SYSCTL) & SRC)); while ((MmioRead32 (MMCHS_SYSCTL) & SRC));
//Poll till card is busy //Poll till card is busy
while (RetryCount < MAX_RETRY_COUNT) { while (RetryCount < MAX_RETRY_COUNT) {
@ -482,7 +482,7 @@ PerformCardIdenfication (
CmdArgument = 0; CmdArgument = 0;
Status = SendCmd(CMD55, CMD55_INT_EN, CmdArgument); Status = SendCmd(CMD55, CMD55_INT_EN, CmdArgument);
if (Status == EFI_SUCCESS) { if (Status == EFI_SUCCESS) {
DEBUG ((EFI_D_INFO, "CMD55 success. CMD55 response: %x\n", MmioRead32(MMCHS_RSP10))); DEBUG ((EFI_D_INFO, "CMD55 success. CMD55 response: %x\n", MmioRead32 (MMCHS_RSP10)));
gCardInfo->CardType = SD_CARD; gCardInfo->CardType = SD_CARD;
} else { } else {
DEBUG ((EFI_D_INFO, "CMD55 fails.\n")); DEBUG ((EFI_D_INFO, "CMD55 fails.\n"));
@ -503,7 +503,7 @@ PerformCardIdenfication (
DEBUG ((EFI_D_INFO, "ACMD41 fails.\n")); DEBUG ((EFI_D_INFO, "ACMD41 fails.\n"));
return Status; return Status;
} }
((UINT32 *) &(gCardInfo->OCRData))[0] = MmioRead32(MMCHS_RSP10); ((UINT32 *) &(gCardInfo->OCRData))[0] = MmioRead32 (MMCHS_RSP10);
DEBUG ((EFI_D_INFO, "SD card detected. ACMD41 OCR: %x\n", ((UINT32 *) &(gCardInfo->OCRData))[0])); DEBUG ((EFI_D_INFO, "SD card detected. ACMD41 OCR: %x\n", ((UINT32 *) &(gCardInfo->OCRData))[0]));
} else if (gCardInfo->CardType == MMC_CARD) { } else if (gCardInfo->CardType == MMC_CARD) {
CmdArgument = 0; CmdArgument = 0;
@ -512,7 +512,7 @@ PerformCardIdenfication (
DEBUG ((EFI_D_INFO, "CMD1 fails.\n")); DEBUG ((EFI_D_INFO, "CMD1 fails.\n"));
return Status; return Status;
} }
Response = MmioRead32(MMCHS_RSP10); Response = MmioRead32 (MMCHS_RSP10);
DEBUG ((EFI_D_INFO, "MMC card detected.. CMD1 response: %x\n", Response)); DEBUG ((EFI_D_INFO, "MMC card detected.. CMD1 response: %x\n", Response));
//NOTE: For now, I am skipping this since I only have an SD card. //NOTE: For now, I am skipping this since I only have an SD card.
@ -556,10 +556,10 @@ PerformCardIdenfication (
return Status; return Status;
} }
DEBUG ((EFI_D_INFO, "CMD2 response: %x %x %x %x\n", MmioRead32(MMCHS_RSP10), MmioRead32(MMCHS_RSP32), MmioRead32(MMCHS_RSP54), MmioRead32(MMCHS_RSP76))); DEBUG ((EFI_D_INFO, "CMD2 response: %x %x %x %x\n", MmioRead32 (MMCHS_RSP10), MmioRead32 (MMCHS_RSP32), MmioRead32 (MMCHS_RSP54), MmioRead32 (MMCHS_RSP76)));
//Parse CID register data. //Parse CID register data.
ParseCardCIDData(MmioRead32(MMCHS_RSP10), MmioRead32(MMCHS_RSP32), MmioRead32(MMCHS_RSP54), MmioRead32(MMCHS_RSP76)); ParseCardCIDData(MmioRead32 (MMCHS_RSP10), MmioRead32 (MMCHS_RSP32), MmioRead32 (MMCHS_RSP54), MmioRead32 (MMCHS_RSP76));
//Read RCA //Read RCA
CmdArgument = 0; CmdArgument = 0;
@ -570,12 +570,12 @@ PerformCardIdenfication (
} }
//Set RCA for the detected card. RCA is CMD3 response. //Set RCA for the detected card. RCA is CMD3 response.
gCardInfo->RCA = (MmioRead32(MMCHS_RSP10) >> 16); gCardInfo->RCA = (MmioRead32 (MMCHS_RSP10) >> 16);
DEBUG ((EFI_D_INFO, "CMD3 response: RCA %x\n", gCardInfo->RCA)); DEBUG ((EFI_D_INFO, "CMD3 response: RCA %x\n", gCardInfo->RCA));
//MMC Bus setting change after card identification. //MMC Bus setting change after card identification.
MmioAnd32(MMCHS_CON, ~OD); MmioAnd32(MMCHS_CON, ~OD);
MmioOr32(MMCHS_HCTL, SDVS_3_0_V); MmioOr32 (MMCHS_HCTL, SDVS_3_0_V);
UpdateMMCHSClkFrequency(CLKD_400KHZ); //Set the clock frequency to 400KHz. UpdateMMCHSClkFrequency(CLKD_400KHZ); //Set the clock frequency to 400KHz.
return EFI_SUCCESS; return EFI_SUCCESS;
@ -599,12 +599,12 @@ GetCardSpecificData (
} }
//Populate 128-bit CSD register data. //Populate 128-bit CSD register data.
((UINT32 *)&(gCardInfo->CSDData))[0] = MmioRead32(MMCHS_RSP10); ((UINT32 *)&(gCardInfo->CSDData))[0] = MmioRead32 (MMCHS_RSP10);
((UINT32 *)&(gCardInfo->CSDData))[1] = MmioRead32(MMCHS_RSP32); ((UINT32 *)&(gCardInfo->CSDData))[1] = MmioRead32 (MMCHS_RSP32);
((UINT32 *)&(gCardInfo->CSDData))[2] = MmioRead32(MMCHS_RSP54); ((UINT32 *)&(gCardInfo->CSDData))[2] = MmioRead32 (MMCHS_RSP54);
((UINT32 *)&(gCardInfo->CSDData))[3] = MmioRead32(MMCHS_RSP76); ((UINT32 *)&(gCardInfo->CSDData))[3] = MmioRead32 (MMCHS_RSP76);
DEBUG ((EFI_D_INFO, "CMD9 response: %x %x %x %x\n", MmioRead32(MMCHS_RSP10), MmioRead32(MMCHS_RSP32), MmioRead32(MMCHS_RSP54), MmioRead32(MMCHS_RSP76))); DEBUG ((EFI_D_INFO, "CMD9 response: %x %x %x %x\n", MmioRead32 (MMCHS_RSP10), MmioRead32 (MMCHS_RSP32), MmioRead32 (MMCHS_RSP54), MmioRead32 (MMCHS_RSP76)));
//Calculate total number of blocks and max. data transfer rate supported by the detected card. //Calculate total number of blocks and max. data transfer rate supported by the detected card.
GetCardConfigurationData(); GetCardConfigurationData();
@ -660,18 +660,18 @@ ReadBlockData(
while (RetryCount < MAX_RETRY_COUNT) { while (RetryCount < MAX_RETRY_COUNT) {
do { do {
//Read Status. //Read Status.
MmcStatus = MmioRead32(MMCHS_STAT); MmcStatus = MmioRead32 (MMCHS_STAT);
} while(MmcStatus == 0); } while(MmcStatus == 0);
//Check if Buffer read ready (BRR) bit is set? //Check if Buffer read ready (BRR) bit is set?
if (MmcStatus & BRR) { if (MmcStatus & BRR) {
//Clear BRR bit //Clear BRR bit
MmioOr32(MMCHS_STAT, BRR); MmioOr32 (MMCHS_STAT, BRR);
//Read block worth of data. //Read block worth of data.
for (Count = 0; Count < DataSize; Count++) { for (Count = 0; Count < DataSize; Count++) {
*DataBuffer++ = MmioRead32(MMCHS_DATA); *DataBuffer++ = MmioRead32 (MMCHS_DATA);
} }
break; break;
} }
@ -702,14 +702,14 @@ WriteBlockData(
while (RetryCount < MAX_RETRY_COUNT) { while (RetryCount < MAX_RETRY_COUNT) {
do { do {
//Read Status. //Read Status.
MmcStatus = MmioRead32(MMCHS_STAT); MmcStatus = MmioRead32 (MMCHS_STAT);
} while(MmcStatus == 0); } while(MmcStatus == 0);
//Check if Buffer write ready (BWR) bit is set? //Check if Buffer write ready (BWR) bit is set?
if (MmcStatus & BWR) { if (MmcStatus & BWR) {
//Clear BWR bit //Clear BWR bit
MmioOr32(MMCHS_STAT, BWR); MmioOr32 (MMCHS_STAT, BWR);
//Write block worth of data. //Write block worth of data.
for (Count = 0; Count < DataSize; Count++) { for (Count = 0; Count < DataSize; Count++) {
@ -759,7 +759,7 @@ TransferBlockData(
while (RetryCount < MAX_RETRY_COUNT) { while (RetryCount < MAX_RETRY_COUNT) {
//Read Status //Read Status
do { do {
MmcStatus = MmioRead32(MMCHS_STAT); MmcStatus = MmioRead32 (MMCHS_STAT);
} while (MmcStatus == 0); } while (MmcStatus == 0);
//Check if Transfer complete (TC) bit is set? //Check if Transfer complete (TC) bit is set?
@ -772,8 +772,8 @@ TransferBlockData(
//There was an error during the data transfer. //There was an error during the data transfer.
//Set SRD bit to 1 and wait until it return to 0x0. //Set SRD bit to 1 and wait until it return to 0x0.
MmioOr32(MMCHS_SYSCTL, SRD); MmioOr32 (MMCHS_SYSCTL, SRD);
while((MmioRead32(MMCHS_SYSCTL) & SRD) != 0x0); while((MmioRead32 (MMCHS_SYSCTL) & SRD) != 0x0);
return EFI_DEVICE_ERROR; return EFI_DEVICE_ERROR;
} }
@ -807,7 +807,7 @@ SdReadWrite (
UINTN CmdArgument = 0; UINTN CmdArgument = 0;
//Check if the data lines are not in use. //Check if the data lines are not in use.
while ((RetryCount++ < MAX_RETRY_COUNT) && ((MmioRead32(MMCHS_PSTATE) & DATI_MASK) != DATI_ALLOWED)); while ((RetryCount++ < MAX_RETRY_COUNT) && ((MmioRead32 (MMCHS_PSTATE) & DATI_MASK) != DATI_ALLOWED));
if (RetryCount == MAX_RETRY_COUNT) { if (RetryCount == MAX_RETRY_COUNT) {
return EFI_TIMEOUT; return EFI_TIMEOUT;
} }

4
Omap35xxPkg/MMCHSDxe/MMCHS.h
View File

@ -32,8 +32,8 @@
#define MAX_RETRY_COUNT 100 #define MAX_RETRY_COUNT 100
#define HCS (0x1UL << 30) //Host capacity support/1 = Supporting high capacity #define HCS BIT30 //Host capacity support/1 = Supporting high capacity
#define CCS (0x1UL << 30) //Card capacity status/1 = High capacity card #define CCS BIT30 //Card capacity status/1 = High capacity card
typedef struct { typedef struct {
UINT32 Reserved0: 7; // 0 UINT32 Reserved0: 7; // 0
UINT32 V170_V195: 1; // 1.70V - 1.95V UINT32 V170_V195: 1; // 1.70V - 1.95V

2
Omap35xxPkg/MMCHSDxe/MMCHS.inf
View File

@ -45,7 +45,7 @@
gEmbeddedExternalDeviceProtocolGuid gEmbeddedExternalDeviceProtocolGuid
[Pcd] [Pcd]
gOmap35xxTokenSpaceGuid.PcdBeagleMMCHS1Base gOmap35xxTokenSpaceGuid.PcdOmap35xxMMCHS1Base
[depex] [depex]
gEmbeddedExternalDeviceProtocolGuid gEmbeddedExternalDeviceProtocolGuid

12
Omap35xxPkg/Omap35xxPkg.dec
View File

@ -38,9 +38,11 @@
[PcdsFeatureFlag.common] [PcdsFeatureFlag.common]
[PcdsFixedAtBuild.common] [PcdsFixedAtBuild.common]
gOmap35xxTokenSpaceGuid.PcdBeagleConsoleUart|3|UINT32|0x00000202 gOmap35xxTokenSpaceGuid.PcdOmap35xxConsoleUart|3|UINT32|0x00000202
gOmap35xxTokenSpaceGuid.PcdBeagleGpmcOffset|0x00000000|UINT32|0x00000203 gOmap35xxTokenSpaceGuid.PcdOmap35xxGpmcOffset|0x00000000|UINT32|0x00000203
gOmap35xxTokenSpaceGuid.PcdBeagleMMCHS1Base|0x00000000|UINT32|0x00000204 gOmap35xxTokenSpaceGuid.PcdOmap35xxMMCHS1Base|0x00000000|UINT32|0x00000204
gOmap35xxTokenSpaceGuid.PcdBeagleArchTimer|3|UINT32|0x00000205 gOmap35xxTokenSpaceGuid.PcdOmap35xxArchTimer|3|UINT32|0x00000205
gOmap35xxTokenSpaceGuid.PcdBeagleFreeTimer|4|UINT32|0x00000206 gOmap35xxTokenSpaceGuid.PcdOmap35xxFreeTimer|4|UINT32|0x00000206
gOmap35xxTokenSpaceGuid.PcdOmap35xxDebugAgentTimer|5|UINT32|0x00000207
gOmap35xxTokenSpaceGuid.PcdDebugAgentTimerFreqNanoSeconds|1|UINT32|0x00000208

10
Omap35xxPkg/Omap35xxPkg.dsc
View File

@ -148,15 +148,15 @@
gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0x80000000 gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0x80000000
gArmTokenSpaceGuid.PcdCpuResetAddress|0x80008000 gArmTokenSpaceGuid.PcdCpuResetAddress|0x80008000
gOmap35xxTokenSpaceGuid.PcdBeagleGpmcOffset|0x6E000000 gOmap35xxTokenSpaceGuid.PcdOmap35xxGpmcOffset|0x6E000000
gOmap35xxTokenSpaceGuid.PcdBeagleMMCHS1Base|0x4809C000 gOmap35xxTokenSpaceGuid.PcdOmap35xxMMCHS1Base|0x4809C000
# Console # Console
gOmap35xxTokenSpaceGuid.PcdBeagleConsoleUart|3 gOmap35xxTokenSpaceGuid.PcdOmap35xxConsoleUart|3
# Timers # Timers
gOmap35xxTokenSpaceGuid.PcdBeagleArchTimer|3 gOmap35xxTokenSpaceGuid.PcdOmap35xxArchTimer|3
gOmap35xxTokenSpaceGuid.PcdBeagleFreeTimer|4 gOmap35xxTokenSpaceGuid.PcdOmap35xxFreeTimer|4
gEmbeddedTokenSpaceGuid.PcdTimerPeriod|100000 gEmbeddedTokenSpaceGuid.PcdTimerPeriod|100000
gEmbeddedTokenSpaceGuid.PcdEmbeddedFdPerformanceCounterPeriodInNanoseconds|77 gEmbeddedTokenSpaceGuid.PcdEmbeddedFdPerformanceCounterPeriodInNanoseconds|77
gEmbeddedTokenSpaceGuid.PcdEmbeddedFdPerformanceCounterFrequencyInHz|13000000 gEmbeddedTokenSpaceGuid.PcdEmbeddedFdPerformanceCounterFrequencyInHz|13000000

41
Omap35xxPkg/PciEmulation/PciEmulation.c
View File

@ -62,6 +62,41 @@ ConfigureUSBHost (
EFI_STATUS Status; EFI_STATUS Status;
UINT8 Data = 0; UINT8 Data = 0;
#if 0
// Take USB host out of force-standby mode
MmioWrite32 (UHH_SYSCONFIG, UHH_SYSCONFIG_MIDLEMODE_NO_STANDBY
| UHH_SYSCONFIG_CLOCKACTIVITY_ON
| UHH_SYSCONFIG_SIDLEMODE_NO_STANDBY
| UHH_SYSCONFIG_ENAWAKEUP_ENABLE
| UHH_SYSCONFIG_AUTOIDLE_ALWAYS_RUN);
MmioWrite32 (UHH_HOSTCONFIG, UHH_HOSTCONFIG_P3_CONNECT_STATUS_DISCONNECT
| UHH_HOSTCONFIG_P2_CONNECT_STATUS_DISCONNECT
| UHH_HOSTCONFIG_P1_CONNECT_STATUS_DISCONNECT
| UHH_HOSTCONFIG_ENA_INCR_ALIGN_DISABLE
| UHH_HOSTCONFIG_ENA_INCR16_ENABLE
| UHH_HOSTCONFIG_ENA_INCR8_ENABLE
| UHH_HOSTCONFIG_ENA_INCR4_ENABLE
| UHH_HOSTCONFIG_AUTOPPD_ON_OVERCUR_EN_ON
| UHH_HOSTCONFIG_P1_ULPI_BYPASS_ULPI_MODE);
// USB reset (GPIO 147 - Port 5 pin 19) output high
MmioAnd32(GPIO5_BASE + GPIO_OE, ~BIT19);
MmioWrite32 (GPIO5_BASE + GPIO_SETDATAOUT, BIT19);
// Get the Power IC protocol.
Status = gBS->LocateProtocol(&gEmbeddedExternalDeviceProtocolGuid, NULL, (VOID **)&gTPS65950);
ASSERT_EFI_ERROR(Status);
//Enable power to the USB host.
Status = gTPS65950->Read(gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID3, LEDEN), 1, &Data);
ASSERT_EFI_ERROR(Status);
//LEDAON & LEDAPWM control the power to the USB host so enable those bits.
Data |= (LEDAON | LEDAPWM);
Status = gTPS65950->Write(gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID3, LEDEN), 1, &Data);
ASSERT_EFI_ERROR(Status);
#else
// Get the Power IC protocol. // Get the Power IC protocol.
Status = gBS->LocateProtocol(&gEmbeddedExternalDeviceProtocolGuid, NULL, (VOID **)&gTPS65950); Status = gBS->LocateProtocol(&gEmbeddedExternalDeviceProtocolGuid, NULL, (VOID **)&gTPS65950);
ASSERT_EFI_ERROR(Status); ASSERT_EFI_ERROR(Status);
@ -91,7 +126,6 @@ ConfigureUSBHost (
// Take USB host out of force-standby mode // Take USB host out of force-standby mode
MmioWrite32 (UHH_SYSCONFIG, UHH_SYSCONFIG_MIDLEMODE_NO_STANDBY MmioWrite32 (UHH_SYSCONFIG, UHH_SYSCONFIG_MIDLEMODE_NO_STANDBY
| UHH_SYSCONFIG_CLOCKACTIVITY_ON | UHH_SYSCONFIG_CLOCKACTIVITY_ON
| UHH_SYSCONFIG_SIDLEMODE_NO_STANDBY
| UHH_SYSCONFIG_ENAWAKEUP_ENABLE | UHH_SYSCONFIG_ENAWAKEUP_ENABLE
| UHH_SYSCONFIG_SOFTRESET | UHH_SYSCONFIG_SOFTRESET
); );
@ -111,6 +145,7 @@ ConfigureUSBHost (
// USB reset output high // USB reset output high
MmioWrite32 (GPIO5_BASE + GPIO_SETDATAOUT, BIT19); MmioWrite32 (GPIO5_BASE + GPIO_SETDATAOUT, BIT19);
#endif
} }
EFI_STATUS EFI_STATUS
@ -544,7 +579,7 @@ PciEmulationEntryPoint (
// Find out the capability register length and number of physical ports. // Find out the capability register length and number of physical ports.
CapabilityLength = MmioRead8(Private->RootBridge.MemoryStart); CapabilityLength = MmioRead8(Private->RootBridge.MemoryStart);
PhysicalPorts = (MmioRead32(Private->RootBridge.MemoryStart + 0x4)) & 0x0000000F; PhysicalPorts = (MmioRead32 (Private->RootBridge.MemoryStart + 0x4)) & 0x0000000F;
// Calculate the total size of the USB registers. // Calculate the total size of the USB registers.
Private->RootBridge.MemorySize = CapabilityLength + (HOST_CONTROLLER_OPERATION_REG_SIZE + ((4 * PhysicalPorts) - 1)); Private->RootBridge.MemorySize = CapabilityLength + (HOST_CONTROLLER_OPERATION_REG_SIZE + ((4 * PhysicalPorts) - 1));
@ -553,7 +588,7 @@ PciEmulationEntryPoint (
// Port Power Control (PPC) bit in the HCSPARAMS register is already set which indicates // Port Power Control (PPC) bit in the HCSPARAMS register is already set which indicates
// host controller implementation includes port power control. // host controller implementation includes port power control.
for (Count = 0; Count < PhysicalPorts; Count++) { for (Count = 0; Count < PhysicalPorts; Count++) {
MmioOr32((Private->RootBridge.MemoryStart + CapabilityLength + HOST_CONTROLLER_OPERATION_REG_SIZE + 4*Count), 0x00001000); MmioOr32 ((Private->RootBridge.MemoryStart + CapabilityLength + HOST_CONTROLLER_OPERATION_REG_SIZE + 4*Count), 0x00001000);
} }
// Create fake PCI config space. // Create fake PCI config space.

6
Omap35xxPkg/TimerDxe/Timer.c
View File

@ -98,7 +98,7 @@ TimerInterruptHandler (
MmioWrite32 (TISR, TISR_CLEAR_ALL); MmioWrite32 (TISR, TISR_CLEAR_ALL);
// Poll interrupt status bits to ensure clearing // Poll interrupt status bits to ensure clearing
while ((MmioRead32(TISR) & TISR_ALL_INTERRUPT_MASK) != TISR_NO_INTERRUPTS_PENDING); while ((MmioRead32 (TISR) & TISR_ALL_INTERRUPT_MASK) != TISR_NO_INTERRUPTS_PENDING);
gBS->RestoreTPL (OriginalTPL); gBS->RestoreTPL (OriginalTPL);
} }
@ -372,7 +372,7 @@ TimerInitialize (
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
// Set up the timer registers // Set up the timer registers
TimerBaseAddress = TimerBase(FixedPcdGet32(PcdBeagleArchTimer)); TimerBaseAddress = TimerBase(FixedPcdGet32(PcdOmap35xxArchTimer));
TISR = TimerBaseAddress + GPTIMER_TISR; TISR = TimerBaseAddress + GPTIMER_TISR;
TCLR = TimerBaseAddress + GPTIMER_TCLR; TCLR = TimerBaseAddress + GPTIMER_TCLR;
TLDR = TimerBaseAddress + GPTIMER_TLDR; TLDR = TimerBaseAddress + GPTIMER_TLDR;
@ -384,7 +384,7 @@ TimerInitialize (
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
// Install interrupt handler // Install interrupt handler
gVector = InterruptVectorForTimer(FixedPcdGet32(PcdBeagleArchTimer)); gVector = InterruptVectorForTimer(FixedPcdGet32(PcdOmap35xxArchTimer));
Status = gInterrupt->RegisterInterruptSource(gInterrupt, gVector, TimerInterruptHandler); Status = gInterrupt->RegisterInterruptSource(gInterrupt, gVector, TimerInterruptHandler);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);

2
Omap35xxPkg/TimerDxe/TimerDxe.inf
View File

@ -52,7 +52,7 @@
[Pcd.common] [Pcd.common]
gEmbeddedTokenSpaceGuid.PcdTimerPeriod gEmbeddedTokenSpaceGuid.PcdTimerPeriod
gEmbeddedTokenSpaceGuid.PcdEmbeddedFdPerformanceCounterPeriodInNanoseconds gEmbeddedTokenSpaceGuid.PcdEmbeddedFdPerformanceCounterPeriodInNanoseconds
gOmap35xxTokenSpaceGuid.PcdBeagleArchTimer gOmap35xxTokenSpaceGuid.PcdOmap35xxArchTimer
[Depex] [Depex]
gHardwareInterruptProtocolGuid gHardwareInterruptProtocolGuid