mirror of https://github.com/acidanthera/audk.git
OvmfPkg/ResetVector: add CreatePageTables4Level macro
Move code to create 4-level page tables to a nasm macro. No functional change. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Message-Id: <20240301074402.98625-4-kraxel@redhat.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Oliver Steffen <osteffen@redhat.com> Cc: Michael Roth <michael.roth@amd.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Tom Lendacky <thomas.lendacky@amd.com> [lersek@redhat.com: turn the "Cc:" message headers from Gerd's on-list posting into "Cc:" tags in the commit message, in order to pacify "PatchCheck.py"]
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@ -63,6 +63,44 @@ BITS 32
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loop .clearPageTablesMemoryLoop
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%endmacro
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;
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; Create page tables for 4-level paging
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;
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; Argument: upper 32 bits of the page table entries
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;
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%macro CreatePageTables4Level 1
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;
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; Top level Page Directory Pointers (1 * 512GB entry)
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;
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mov dword[PT_ADDR (0)], PT_ADDR (0x1000) + PAGE_PDE_DIRECTORY_ATTR
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mov dword[PT_ADDR (4)], %1
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;
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; Next level Page Directory Pointers (4 * 1GB entries => 4GB)
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;
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mov dword[PT_ADDR (0x1000)], PT_ADDR (0x2000) + PAGE_PDE_DIRECTORY_ATTR
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mov dword[PT_ADDR (0x1004)], %1
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mov dword[PT_ADDR (0x1008)], PT_ADDR (0x3000) + PAGE_PDE_DIRECTORY_ATTR
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mov dword[PT_ADDR (0x100C)], %1
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mov dword[PT_ADDR (0x1010)], PT_ADDR (0x4000) + PAGE_PDE_DIRECTORY_ATTR
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mov dword[PT_ADDR (0x1014)], %1
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mov dword[PT_ADDR (0x1018)], PT_ADDR (0x5000) + PAGE_PDE_DIRECTORY_ATTR
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mov dword[PT_ADDR (0x101C)], %1
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;
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; Page Table Entries (2048 * 2MB entries => 4GB)
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;
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mov ecx, 0x800
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.pageTableEntriesLoop4Level:
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mov eax, ecx
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dec eax
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shl eax, 21
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add eax, PAGE_PDE_LARGEPAGE_ATTR
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mov dword[ecx * 8 + PT_ADDR (0x2000 - 8)], eax
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mov dword[(ecx * 8 + PT_ADDR (0x2000 - 8)) + 4], %1
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loop .pageTableEntriesLoop4Level
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%endmacro
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;
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; Modified: EAX, EBX, ECX, EDX
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;
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@ -88,37 +126,7 @@ SetCr3ForPageTables64:
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ClearOvmfPageTables:
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ClearOvmfPageTables
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;
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; Top level Page Directory Pointers (1 * 512GB entry)
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;
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mov dword[PT_ADDR (0)], PT_ADDR (0x1000) + PAGE_PDE_DIRECTORY_ATTR
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mov dword[PT_ADDR (4)], edx
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;
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; Next level Page Directory Pointers (4 * 1GB entries => 4GB)
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;
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mov dword[PT_ADDR (0x1000)], PT_ADDR (0x2000) + PAGE_PDE_DIRECTORY_ATTR
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mov dword[PT_ADDR (0x1004)], edx
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mov dword[PT_ADDR (0x1008)], PT_ADDR (0x3000) + PAGE_PDE_DIRECTORY_ATTR
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mov dword[PT_ADDR (0x100C)], edx
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mov dword[PT_ADDR (0x1010)], PT_ADDR (0x4000) + PAGE_PDE_DIRECTORY_ATTR
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mov dword[PT_ADDR (0x1014)], edx
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mov dword[PT_ADDR (0x1018)], PT_ADDR (0x5000) + PAGE_PDE_DIRECTORY_ATTR
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mov dword[PT_ADDR (0x101C)], edx
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;
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; Page Table Entries (2048 * 2MB entries => 4GB)
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;
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mov ecx, 0x800
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pageTableEntriesLoop:
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mov eax, ecx
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dec eax
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shl eax, 21
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add eax, PAGE_PDE_LARGEPAGE_ATTR
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mov [ecx * 8 + PT_ADDR (0x2000 - 8)], eax
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mov [(ecx * 8 + PT_ADDR (0x2000 - 8)) + 4], edx
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loop pageTableEntriesLoop
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CreatePageTables4Level edx
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; Clear the C-bit from the GHCB page if the SEV-ES is enabled.
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OneTimeCall SevClearPageEncMaskForGhcbPage
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