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UefiCpuPkg/Include/Register/ArchitecturalMsr.h: Change structure definition. 

V3 changes include:
  1. Keep ReservedX not change if bit info not changed for this field.

V2 changes include:
  1. Use X in ReservedX fields from totally new value if MSR structure definition changed.
     For example, if in current structure, the max reserved variable is Reserved2, in new
     definition, reserved variable is begin with Reserved3.

V1 Changes includes:
  1. Change fields which is reserved in old version: MSR_IA32_RTIT_CTL_REGISTER

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
This commit is contained in:
Eric Dong 2018-09-25 08:32:31 +08:00
parent 140d713175
commit 4382394aa9
1 changed files with 12 additions and 2 deletions
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14
UefiCpuPkg/Include/Register/ArchitecturalMsr.h
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@ -4647,7 +4647,14 @@ typedef union {
/// [Bit 3] User.
///
UINT32 User:1;
UINT32 Reserved1:2;
///
/// [Bit 4] PwrEvtEn.
///
UINT32 PwrEvtEn:1;
///
/// [Bit 5] FUPonPTW.
///
UINT32 FUPonPTW:1;
///
/// [Bit 6] FabricEn. If (CPUID.(EAX=07H, ECX=0):ECX[3] = 1).
///
@ -4672,7 +4679,10 @@ typedef union {
/// [Bit 11] DisRETC.
///
UINT32 DisRETC:1;
UINT32 Reserved2:1;
///
/// [Bit 12] PTWEn.
///
UINT32 PTWEn:1;
///
/// [Bit 13] BranchEn.
///