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ArmPkg: Minor coding style changes 

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11993 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin 2011-07-06 16:35:30 +00:00
parent d269095b71
commit 438311a3bd
5 changed files with 38 additions and 30 deletions
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6
ArmPkg/Drivers/CpuPei/CpuPei.c
View File

@ -47,7 +47,7 @@ Abstract:
#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED #define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
EFI_STATUS EFI_STATUS
FindMainMemory( FindMainMemory (
OUT UINT32 *PhysicalBase, OUT UINT32 *PhysicalBase,
OUT UINT32 *Length OUT UINT32 *Length
) )
@ -71,7 +71,9 @@ FindMainMemory(
} }
VOID VOID
ConfigureMmu ( VOID ) ConfigureMmu (
VOID
)
{ {
EFI_STATUS Status; EFI_STATUS Status;
UINTN Idx; UINTN Idx;

21
ArmPkg/Drivers/PL390Gic/PL390GicNonSec.c
View File

@ -12,6 +12,7 @@
* *
**/ **/
#include <Uefi.h>
#include <Library/IoLib.h> #include <Library/IoLib.h>
#include <Drivers/PL390Gic.h> #include <Drivers/PL390Gic.h>
@ -26,7 +27,7 @@ PL390GicEnableInterruptInterface (
* Enable the CPU interface in Non-Secure world * Enable the CPU interface in Non-Secure world
* Note: The ICCICR register is banked when Security extensions are implemented * Note: The ICCICR register is banked when Security extensions are implemented
*/ */
MmioWrite32(GicInterruptInterfaceBase + GIC_ICCICR,0x00000001); MmioWrite32 (GicInterruptInterfaceBase + GIC_ICCICR,0x00000001);
} }
VOID VOID
@ -39,7 +40,7 @@ PL390GicEnableDistributor (
* Enable GIC distributor in Non-Secure world. * Enable GIC distributor in Non-Secure world.
* Note: The ICDDCR register is banked when Security extensions are implemented * Note: The ICDDCR register is banked when Security extensions are implemented
*/ */
MmioWrite32(GicDistributorBase + GIC_ICDDCR, 0x00000001); MmioWrite32 (GicDistributorBase + GIC_ICDDCR, 0x00000001);
} }
VOID VOID
@ -50,7 +51,7 @@ PL390GicSendSgiTo (
IN INTN CPUTargetList IN INTN CPUTargetList
) )
{ {
MmioWrite32(GicDistributorBase + GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16)); MmioWrite32 (GicDistributorBase + GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16));
} }
UINT32 UINT32
@ -62,12 +63,12 @@ PL390GicAcknowledgeSgiFrom (
{ {
INTN InterruptId; INTN InterruptId;
InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR); InterruptId = MmioRead32 (GicInterruptInterfaceBase + GIC_ICCIAR);
//Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID // Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
if (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) { if (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) {
//Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR // Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId); MmioWrite32 (GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
return 1; return 1;
} else { } else {
return 0; return 0;
@ -86,10 +87,10 @@ PL390GicAcknowledgeSgi2From (
InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR); InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
//Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID // Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
if((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) { if((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) {
//Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR // Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId); MmioWrite32 (GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
return 1; return 1;
} else { } else {
return 0; return 0;

1
ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLib.inf
View File

@ -42,6 +42,7 @@
MdePkg/MdePkg.dec MdePkg/MdePkg.dec
[LibraryClasses] [LibraryClasses]
IoLib
MemoryAllocationLib MemoryAllocationLib
[Protocols] [Protocols]

1
ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLibPrePi.inf
View File

@ -40,6 +40,7 @@
MdePkg/MdePkg.dec MdePkg/MdePkg.dec
[LibraryClasses] [LibraryClasses]
IoLib
PrePiLib PrePiLib
[Protocols] [Protocols]

3
ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLibSec.inf
View File

@ -36,6 +36,9 @@
ArmPkg/ArmPkg.dec ArmPkg/ArmPkg.dec
MdePkg/MdePkg.dec MdePkg/MdePkg.dec
[LibraryClasses]
IoLib
[Protocols] [Protocols]
gEfiCpuArchProtocolGuid gEfiCpuArchProtocolGuid