Update CpuSleep() for IPF.

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@8315 6f19259b-4bc3-4df7-8a09-765794883524

MdePkg/Library/BaseCpuLib/Ipf/CpuSleep.c

@@ -1,7 +1,7 @@
 /** @file
   Base Library CPU functions for Itanium
 
-  Copyright (c) 2006 - 2008, Intel Corporation<BR>
+  Copyright (c) 2006 - 2009, Intel Corporation<BR>
   All rights reserved. This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
   which accompanies this distribution.  The full text of the license may be found at
@@ -13,6 +13,7 @@
 **/
 
 #include <Library/PalLib.h>
+#include <Library/BaseLib.h>
 
 /**
   Places the CPU in a sleep state until an interrupt is received.
@@ -28,5 +29,38 @@ CpuSleep (
   VOID
   )
 {
-  PalCall (29, 0, 0, 0);
+  UINT64  Tpr;
+
+  //
+  // It is the TPR register that controls if external interrupt would bring processor in LIGHT HALT low-power state
+  // back to normal state. PAL_HALT_LIGHT does not depend on PSR setting.
+  // So here if interrupts are disabled (via PSR.i), TRP.mmi needs to be set to prevent processor being interrupted by external interrupts.
+  // If interrupts are enabled, then just use current TRP setting.
+  //
+  if (GetInterruptState ()) {
+    //
+    // If interrupts are enabled, then call PAL_HALT_LIGHT with the current TPR setting.
+    //
+    PalCall (PAL_HALT_LIGHT, 0, 0, 0);
+  } else {
+    //
+    // If interrupts are disabled on entry, then mask all interrupts in TPR before calling PAL_HALT_LIGHT.
+    //
+
+    //
+    // Save TPR
+    //
+    Tpr = AsmReadTpr();
+    //
+    // Set TPR.mmi to mask all external interrupts
+    //
+    AsmWriteTpr (BIT16 | Tpr);
+
+    PalCall (PAL_HALT_LIGHT, 0, 0, 0);
+
+    //
+    // Restore TPR
+    //
+    AsmWriteTpr (Tpr);
+  }
 }