mirror of https://github.com/acidanthera/audk.git
MtrrDebugPrintAllMtrrs() should loop until the max physical address is reached.
GetMemoryCacheTypeFromMtrrType () should return the default memory type instead of UC type for MTRR_CACHE_INVALID_TYPE. Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15053 6f19259b-4bc3-4df7-8a09-765794883524
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@ -1,7 +1,7 @@
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/** @file
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MTRR setting library
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Copyright (c) 2008 - 2012, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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@ -808,7 +808,7 @@ GetMemoryCacheTypeFromMtrrType (
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// MtrrType is MTRR_CACHE_INVALID_TYPE, that means
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// no mtrr covers the range
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//
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return CacheUncacheable;
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return MtrrGetDefaultMemoryType ();
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}
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}
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@ -1609,6 +1609,12 @@ MtrrDebugPrintAllMtrrs (
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VariableMtrrCount = GetVariableMtrrCount ();
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Limit = BIT36 - 1;
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AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
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if (RegEax >= 0x80000008) {
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AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
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Limit = LShiftU64 (1, RegEax & 0xff) - 1;
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}
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Base = BASE_1MB;
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PreviousMemoryType = MTRR_CACHE_INVALID_TYPE;
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do {
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@ -1627,12 +1633,6 @@ MtrrDebugPrintAllMtrrs (
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RangeBase = BASE_1MB;
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NoRangeBase = BASE_1MB;
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Limit = BIT36 - 1;
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AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
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if (RegEax >= 0x80000008) {
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AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
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Limit = LShiftU64 (1, RegEax & 0xff) - 1;
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}
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RangeLimit = Limit;
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NoRangeLimit = Limit;
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@ -1676,7 +1676,7 @@ MtrrDebugPrintAllMtrrs (
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} else {
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Base = NoRangeLimit + 1;
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}
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} while (Found);
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} while (Base < Limit);
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DEBUG((DEBUG_CACHE, "%016lx\n\n", Base - 1));
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);
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}
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@ -1,7 +1,7 @@
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## @file
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# MTRR library provides API for MTRR operation
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#
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# Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
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# Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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@ -38,4 +38,5 @@
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BaseMemoryLib
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BaseLib
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CpuLib
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DebugLib
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