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MtrrDebugPrintAllMtrrs() should loop until the max physical address is reached.

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GetMemoryCacheTypeFromMtrrType () should return the default memory type instead of UC type for MTRR_CACHE_INVALID_TYPE.

Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15053 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Jeff Fan 2014-01-07 06:24:16 +00:00 committed by vanjeff
parent 31c2a2c7c0
commit 44c8400a7d
2 changed files with 11 additions and 10 deletions
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18
UefiCpuPkg/Library/MtrrLib/MtrrLib.c
View File

@ -1,7 +1,7 @@
/** @file /** @file
MTRR setting library MTRR setting library
Copyright (c) 2008 - 2012, Intel Corporation. All rights reserved.<BR> Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
@ -808,7 +808,7 @@ GetMemoryCacheTypeFromMtrrType (
// MtrrType is MTRR_CACHE_INVALID_TYPE, that means // MtrrType is MTRR_CACHE_INVALID_TYPE, that means
// no mtrr covers the range // no mtrr covers the range
// //
return CacheUncacheable; return MtrrGetDefaultMemoryType ();
} }
} }
@ -1609,6 +1609,12 @@ MtrrDebugPrintAllMtrrs (
VariableMtrrCount = GetVariableMtrrCount (); VariableMtrrCount = GetVariableMtrrCount ();
Limit = BIT36 - 1;
AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
if (RegEax >= 0x80000008) {
AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
Limit = LShiftU64 (1, RegEax & 0xff) - 1;
}
Base = BASE_1MB; Base = BASE_1MB;
PreviousMemoryType = MTRR_CACHE_INVALID_TYPE; PreviousMemoryType = MTRR_CACHE_INVALID_TYPE;
do { do {
@ -1627,12 +1633,6 @@ MtrrDebugPrintAllMtrrs (
RangeBase = BASE_1MB; RangeBase = BASE_1MB;
NoRangeBase = BASE_1MB; NoRangeBase = BASE_1MB;
Limit = BIT36 - 1;
AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
if (RegEax >= 0x80000008) {
AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
Limit = LShiftU64 (1, RegEax & 0xff) - 1;
}
RangeLimit = Limit; RangeLimit = Limit;
NoRangeLimit = Limit; NoRangeLimit = Limit;
@ -1676,7 +1676,7 @@ MtrrDebugPrintAllMtrrs (
} else { } else {
Base = NoRangeLimit + 1; Base = NoRangeLimit + 1;
} }
} while (Found); } while (Base < Limit);
DEBUG((DEBUG_CACHE, "%016lx\n\n", Base - 1)); DEBUG((DEBUG_CACHE, "%016lx\n\n", Base - 1));
); );
} }

3
UefiCpuPkg/Library/MtrrLib/MtrrLib.inf
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@ -1,7 +1,7 @@
## @file ## @file
# MTRR library provides API for MTRR operation # MTRR library provides API for MTRR operation
# #
# Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR> # Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials # This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License # are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at # which accompanies this distribution. The full text of the license may be found at
@ -38,4 +38,5 @@
BaseMemoryLib BaseMemoryLib
BaseLib BaseLib
CpuLib CpuLib
DebugLib