mirror of https://github.com/acidanthera/audk.git
EmbeddedPkg/MmcDxe: Add non-DDR timing mode support
Only DDR mode is support for 8bit mode currently. Add non-DDR case when configuring ECSD. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jun Nie <jun.nie@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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03a5572bed
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@ -254,7 +254,7 @@ InitializeEmmcDevice (
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EFI_MMC_HOST_PROTOCOL *Host;
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EFI_MMC_HOST_PROTOCOL *Host;
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EFI_STATUS Status = EFI_SUCCESS;
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EFI_STATUS Status = EFI_SUCCESS;
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ECSD *ECSDData;
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ECSD *ECSDData;
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UINT32 BusClockFreq, Idx;
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UINT32 BusClockFreq, Idx, BusMode;
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UINT32 TimingMode[4] = {EMMCHS52DDR1V2, EMMCHS52DDR1V8, EMMCHS52, EMMCHS26};
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UINT32 TimingMode[4] = {EMMCHS52DDR1V2, EMMCHS52DDR1V8, EMMCHS52, EMMCHS26};
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Host = MmcHostInstance->MmcHost;
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Host = MmcHostInstance->MmcHost;
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@ -286,7 +286,19 @@ InitializeEmmcDevice (
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}
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}
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Status = Host->SetIos (Host, BusClockFreq, 8, TimingMode[Idx]);
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Status = Host->SetIos (Host, BusClockFreq, 8, TimingMode[Idx]);
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if (!EFI_ERROR (Status)) {
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if (!EFI_ERROR (Status)) {
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Status = EmmcSetEXTCSD (MmcHostInstance, EXTCSD_BUS_WIDTH, EMMC_BUS_WIDTH_DDR_8BIT);
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switch (TimingMode[Idx]) {
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case EMMCHS52DDR1V2:
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case EMMCHS52DDR1V8:
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BusMode = EMMC_BUS_WIDTH_DDR_8BIT;
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break;
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case EMMCHS52:
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case EMMCHS26:
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BusMode = EMMC_BUS_WIDTH_8BIT;
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break;
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default:
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return EFI_UNSUPPORTED;
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}
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Status = EmmcSetEXTCSD (MmcHostInstance, EXTCSD_BUS_WIDTH, BusMode);
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if (EFI_ERROR (Status)) {
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if (EFI_ERROR (Status)) {
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DEBUG ((DEBUG_ERROR, "InitializeEmmcDevice(): Failed to set EXTCSD bus width, Status:%r\n", Status));
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DEBUG ((DEBUG_ERROR, "InitializeEmmcDevice(): Failed to set EXTCSD bus width, Status:%r\n", Status));
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}
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}
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