mirror of https://github.com/acidanthera/audk.git
UefiCpuPkg/PiSmmCpuDxeSmm: eliminate "gSmmJmpAddr" and related DBs
The IA32 version of "SmmInit.nasm" does not need "gSmmJmpAddr" at all (its PiSmmCpuSmmInitFixupAddress() variant doesn't do anything either). We can simply use the NASM syntax for the following Mixed-Size Jump: > jmp PROTECT_MODE_CS : dword @32bit The generated object code for the instruction is unchanged: > 00000182 66EA5A0000000800 jmp dword 0x8:0x5a (The NASM manual explains that putting the DWORD prefix after the colon ":" reflects the intent better, since it is the offset that is a DWORD. Thus, that's what I used. However, both syntaxes are interchangeable, hence the ndisasm output.) The X64 version of "SmmInit.nasm" appears to require "gSmmJmpAddr"; however that's accidental, not inherent: - Bring LONG_MODE_CODE_SEGMENT from "UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h" to "SmmInit.nasm" as LONG_MODE_CS, same as PROTECT_MODE_CODE_SEGMENT was brought to the IA32 version as PROTECT_MODE_CS earlier. - Apply the NASM-native Mixed-Size Jump syntax again, but jump to the fixed zero offset in LONG_MODE_CS. This will produce no relocation record at all. Add a label after the instruction. - Modify PiSmmCpuSmmInitFixupAddress() to patch the jump target backwards from the label. Because we modify the DWORD offset with a DWORD access, the segment selector is unharmed in the instruction, and we need not set it from PiCpuSmmEntry(). According to "objdump --reloc", the X64 version undergoes only the following relocations, after this patch: > RELOCATION RECORDS FOR [.text]: > OFFSET TYPE VALUE > 0000000000000095 R_X86_64_PC32 SmmInitHandler-0x0000000000000004 > 00000000000000e0 R_X86_64_PC32 mRebasedFlag-0x0000000000000004 > 00000000000000ea R_X86_64_PC32 mSmmRelocationOriginalAddress-0x0000000000000004 Therefore the patch does not regress <https://bugzilla.tianocore.org/show_bug.cgi?id=849> ("Enable XCODE5 tool chain for UefiCpuPkg with nasm source code"). Cc: Eric Dong <eric.dong@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=866 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
This commit is contained in:
Laszlo Ersek
parent
f0053e837a
commit
456c4ccab2
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@ -25,7 +25,6 @@ extern ASM_PFX(mSmmRelocationOriginalAddress)
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global ASM_PFX(gPatchSmmCr3)
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global ASM_PFX(gPatchSmmCr4)
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global ASM_PFX(gPatchSmmCr0)
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global ASM_PFX(gSmmJmpAddr)
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global ASM_PFX(gSmmInitStack)
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global ASM_PFX(gcSmiInitGdtr)
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global ASM_PFX(gcSmmInitSize)
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@ -64,10 +63,7 @@ ASM_PFX(gPatchSmmCr4):
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ASM_PFX(gPatchSmmCr0):
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mov di, PROTECT_MODE_DS
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mov cr0, eax
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DB 0x66, 0xea ; jmp far [ptr48]
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ASM_PFX(gSmmJmpAddr):
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DD @32bit
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DW PROTECT_MODE_CS
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jmp PROTECT_MODE_CS : dword @32bit
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BITS 32
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@32bit:
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@ -569,13 +569,6 @@ PiCpuSmmEntry (
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EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_PC_SMM_INIT
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);
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//
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// Fix segment address of the long-mode-switch jump
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//
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if (sizeof (UINTN) == sizeof (UINT64)) {
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gSmmJmpAddr.Segment = LONG_MODE_CODE_SEGMENT;
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}
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//
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// Find out SMRR Base and SMRR Size
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//
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@ -295,17 +295,6 @@ WriteSaveStateRegister (
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IN CONST VOID *Buffer
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);
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//
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//
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//
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typedef struct {
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UINT32 Offset;
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UINT16 Segment;
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UINT16 Reserved;
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} IA32_FAR_ADDRESS;
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extern IA32_FAR_ADDRESS gSmmJmpAddr;
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extern CONST UINT8 gcSmmInitTemplate[];
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extern CONST UINT16 gcSmmInitSize;
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X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr0;
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@ -25,7 +25,6 @@ extern ASM_PFX(mSmmRelocationOriginalAddress)
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global ASM_PFX(gPatchSmmCr3)
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global ASM_PFX(gPatchSmmCr4)
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global ASM_PFX(gPatchSmmCr0)
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global ASM_PFX(gSmmJmpAddr)
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global ASM_PFX(gSmmInitStack)
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global ASM_PFX(gcSmiInitGdtr)
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global ASM_PFX(gcSmmInitSize)
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@ -33,6 +32,8 @@ global ASM_PFX(gcSmmInitTemplate)
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global ASM_PFX(mRebasedFlagAddr32)
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global ASM_PFX(mSmmRelocationOriginalAddressPtr32)
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%define LONG_MODE_CS 0x38
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DEFAULT REL
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SECTION .text
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@ -66,8 +67,8 @@ ASM_PFX(gPatchSmmCr4):
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mov eax, strict dword 0 ; source operand will be patched
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ASM_PFX(gPatchSmmCr0):
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mov cr0, eax ; enable protected mode & paging
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DB 0x66, 0xea ; far jmp to long mode
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ASM_PFX(gSmmJmpAddr): DQ 0;@LongMode
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jmp LONG_MODE_CS : dword 0 ; offset will be patched to @LongMode
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@PatchLongModeOffset:
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BITS 64
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@LongMode: ; long-mode starts here
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@ -141,8 +142,8 @@ ASM_PFX(mSmmRelocationOriginalAddressPtr32): dd 0
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global ASM_PFX(PiSmmCpuSmmInitFixupAddress)
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ASM_PFX(PiSmmCpuSmmInitFixupAddress):
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lea rax, [@LongMode]
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lea rcx, [ASM_PFX(gSmmJmpAddr)]
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mov qword [rcx], rax
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lea rcx, [@PatchLongModeOffset - 6]
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mov dword [rcx], eax
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lea rax, [ASM_PFX(SmmStartup)]
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lea rcx, [@L1]
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