mirror of https://github.com/acidanthera/audk.git
MdeModulePkg/PciBusDxe: Improve the flow of testing support attributes
https://bugzilla.tianocore.org/show_bug.cgi?id=3635 Currently, in order to test the supported attributes, the PciTestSupportedAttribute() will set the command register to 0x27 (EFI_PCI_COMMAND_IO_SPACE, EFI_PCI_COMMAND_MEMORY_SPACE, EFI_PCI_COMMAND_BUS_MASTER, EFI_PCI_COMMAND_VGA_PALETTE_SNOOP) firstly, and then read back to check whether these attributes are set successfully in the device. This will cause the other enabled bits (other than EFI_PCI_COMMAND_IO_SPACE,EFI_PCI_COMMAND_MEMORY_SPACE, EFI_PCI_COMMAND_BUS_MASTER,EFI_PCI_COMMAND_VGA_PALETTE_SNOOP) be cleared for a short of time This patch fixes this issue by keeping the origina enabled bits when setting 0x27. Signed-off-by: xueshengfeng <xueshengfeng@byosoft.com.cn> Reviewed-by: Ray <ray.ni@intel.com>
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@ -933,6 +933,7 @@ PciTestSupportedAttribute (
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{
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{
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EFI_TPL OldTpl;
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EFI_TPL OldTpl;
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UINT16 CommandValue;
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//
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//
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// Preserve the original value
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// Preserve the original value
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@ -943,10 +944,12 @@ PciTestSupportedAttribute (
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// Raise TPL to high level to disable timer interrupt while the BAR is probed
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// Raise TPL to high level to disable timer interrupt while the BAR is probed
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//
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//
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OldTpl = gBS->RaiseTPL (TPL_HIGH_LEVEL);
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OldTpl = gBS->RaiseTPL (TPL_HIGH_LEVEL);
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CommandValue = *Command | *OldCommand;
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PCI_SET_COMMAND_REGISTER (PciIoDevice, *Command);
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PCI_SET_COMMAND_REGISTER (PciIoDevice, CommandValue);
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PCI_READ_COMMAND_REGISTER (PciIoDevice, Command);
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PCI_READ_COMMAND_REGISTER (PciIoDevice, &CommandValue);
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*Command = *Command & CommandValue;
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//
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//
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// Write back the original value
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// Write back the original value
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//
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//
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