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ArmPlatformPkg/PrePeiCore: Reserve some memory on the top of the stack for Global Variables in XIP code 

The size of this memory is controlled by a PCD. The Global Variable in this regsion are defined by their offset.

This memory region can be use to store the PEI Services Table Pointer.
Update the PeiServicesTablePointerLib to use this region instead of PcdPeiServicePtrAddr.



git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11803 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin 2011-06-11 12:03:00 +00:00
parent 936eff09c3
commit 47a8e12fe1
10 changed files with 56 additions and 28 deletions
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11
ArmPlatformPkg/ArmPlatformPkg.dec
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@ -46,8 +46,6 @@
# Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor. # Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.
gArmPlatformTokenSpaceGuid.PcdMPCoreSupport|0|UINT32|0x00000002 gArmPlatformTokenSpaceGuid.PcdMPCoreSupport|0|UINT32|0x00000002
gArmPlatformTokenSpaceGuid.PcdPeiServicePtrAddr|0|UINT32|0x00000003
# Stack for CPU Cores in Secure Mode # Stack for CPU Cores in Secure Mode
gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0|UINT32|0x00000004 gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0|UINT32|0x00000004
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecStackSize|0|UINT32|0x00000005 gArmPlatformTokenSpaceGuid.PcdCPUCoreSecStackSize|0|UINT32|0x00000005
@ -65,6 +63,15 @@
# Size of the region reserved for fixed address allocations (Reserved 128MB by default) # Size of the region reserved for fixed address allocations (Reserved 128MB by default)
gArmPlatformTokenSpaceGuid.PcdSystemMemoryFixRegionSize|0x08000000|UINT32|0x00000014 gArmPlatformTokenSpaceGuid.PcdSystemMemoryFixRegionSize|0x08000000|UINT32|0x00000014
# Size to reserve in the primary core stack for PEI Global Variables
# = sizeof(UINTN) /* PcdPeiServicePtr or HobListPtr */
gArmPlatformTokenSpaceGuid.PcdPeiGlobalVariableSize|0x4|UINT32|0x00000016
# PeiServicePtr and HobListPtr shares the same location in the PEI Global Variable list
# PeiServicePtr is only valid with PEI Core and HobListPtr only when the PEI Core is skipped.
gArmPlatformTokenSpaceGuid.PcdPeiServicePtrGlobalOffset|0x4|UINT32|0x00000017
gArmPlatformTokenSpaceGuid.PcdHobListPtrGlobalOffset|0x4|UINT32|0x00000018
# #
# ARM Primecells # ARM Primecells
# #

1
ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A8.dsc
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@ -348,7 +348,6 @@
# Stack for CPU Cores in Non Secure Mode # Stack for CPU Cores in Non Secure Mode
gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase|0x48000000 # Top of SEC Stack for Normal World gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase|0x48000000 # Top of SEC Stack for Normal World
gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize|0x20000 # Size of SEC Stack for Normal World gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize|0x20000 # Size of SEC Stack for Normal World
gArmPlatformTokenSpaceGuid.PcdPeiServicePtrAddr|0x48020004 # Pei Services Ptr just above stack
# Non Sec UEFI Firmware: These two PCDs must match PcdFlashFvMainBase/PcdFlashFvMainSize # Non Sec UEFI Firmware: These two PCDs must match PcdFlashFvMainBase/PcdFlashFvMainSize
gArmTokenSpaceGuid.PcdNormalFdBaseAddress|0x40050000 # Must be equal to gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase gArmTokenSpaceGuid.PcdNormalFdBaseAddress|0x40050000 # Must be equal to gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase

1
ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A9x2.dsc
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@ -352,7 +352,6 @@
# Stacks for MPCores in Normal World # Stacks for MPCores in Normal World
gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase|0x48000000 # Top of SEC Stack for Normal World gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase|0x48000000 # Top of SEC Stack for Normal World
gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize|0x20000 # Stack for each of the 4 CPU cores gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize|0x20000 # Stack for each of the 4 CPU cores
gArmPlatformTokenSpaceGuid.PcdPeiServicePtrAddr|0x48020004 # Pei Services Ptr just above stack
# Non Sec UEFI Firmware: These two PCDs must match PcdFlashFvMainBase/PcdFlashFvMainSize # Non Sec UEFI Firmware: These two PCDs must match PcdFlashFvMainBase/PcdFlashFvMainSize
gArmTokenSpaceGuid.PcdNormalFdBaseAddress|0x40050000 # Must be equal to gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase gArmTokenSpaceGuid.PcdNormalFdBaseAddress|0x40050000 # Must be equal to gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase

1
ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.dsc
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@ -383,7 +383,6 @@
# Stacks for MPCores in Normal World # Stacks for MPCores in Normal World
gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase|0x48000000 # Top of SEC Stack for Normal World gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase|0x48000000 # Top of SEC Stack for Normal World
gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize|0x00020000 # Stack for each of the 4 CPU cores gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize|0x00020000 # Stack for each of the 4 CPU cores
gArmPlatformTokenSpaceGuid.PcdPeiServicePtrAddr|0x48020004 # pei services ptr just above stack. Overlapped with the stack of CoreId 1
# System Memory (1GB) # System Memory (1GB)

4
ArmPlatformPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointer.c
View File

@ -39,7 +39,7 @@ SetPeiServicesTablePointer (
UINTN *PeiPtrLoc; UINTN *PeiPtrLoc;
ASSERT (PeiServicesTablePointer != NULL); ASSERT (PeiServicesTablePointer != NULL);
PeiPtrLoc = (UINTN *)(UINTN)PcdGet32(PcdPeiServicePtrAddr); PeiPtrLoc = (UINTN *)(UINTN)(PcdGet32 (PcdCPUCoresNonSecStackBase) + (PcdGet32 (PcdCPUCoresNonSecStackSize) / 2) - PcdGet32 (PcdPeiServicePtrGlobalOffset));
*PeiPtrLoc = (UINTN)PeiServicesTablePointer; *PeiPtrLoc = (UINTN)PeiServicesTablePointer;
} }
@ -63,7 +63,7 @@ GetPeiServicesTablePointer (
{ {
UINTN *PeiPtrLoc; UINTN *PeiPtrLoc;
PeiPtrLoc = (UINTN *)(UINTN)PcdGet32(PcdPeiServicePtrAddr); PeiPtrLoc = (UINTN *)(UINTN)(PcdGet32 (PcdCPUCoresNonSecStackBase) + (PcdGet32 (PcdCPUCoresNonSecStackSize) / 2) - PcdGet32 (PcdPeiServicePtrGlobalOffset));
return (CONST EFI_PEI_SERVICES **)*PeiPtrLoc; return (CONST EFI_PEI_SERVICES **)*PeiPtrLoc;
} }

5
ArmPlatformPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
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@ -40,4 +40,7 @@
DebugLib DebugLib
[Pcd] [Pcd]
gArmPlatformTokenSpaceGuid.PcdPeiServicePtrAddr gArmPlatformTokenSpaceGuid.PcdPeiServicePtrGlobalOffset
gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase
gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize

33
ArmPlatformPkg/PrePeiCore/PrePeiCoreEntryPoint.S
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@ -1,22 +1,21 @@
// //
// Copyright (c) 2011, ARM Limited. All rights reserved. // Copyright (c) 2011, ARM Limited. All rights reserved.
// //
# This program and the accompanying materials // This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License // are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at // which accompanies this distribution. The full text of the license may be found at
# http:#opensource.org/licenses/bsd-license.php // http://opensource.org/licenses/bsd-license.php
# //
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
# //
# //
#include <AsmMacroIoLib.h> #include <AsmMacroIoLib.h>
#include <Base.h> #include <Base.h>
#include <Library/PcdLib.h> #include <Library/PcdLib.h>
#include <AutoGen.h> #include <AutoGen.h>
#start of the code section
.text .text
.align 3 .align 3
@ -45,9 +44,17 @@ _SetupStack:
add r3,r3,r2,LSR #1 @ r3 = stack_offset + (stack_size/2) <-- the top half is for the heap add r3,r3,r2,LSR #1 @ r3 = stack_offset + (stack_size/2) <-- the top half is for the heap
mov sp, r3 mov sp, r3
# lr points to area in reset vector block containing PEI core address. lr needs to # Only allocate memory in top of the primary core stack
# be saved from the beginning as the _ModuleEntryPoint could call helper functions cmp r0, #0
# that will overwrite 'lr' bne _PrepareArguments
_AllocateGlobalPeiVariables:
# Reserve top of the stack for Global PEI Variables (eg: PeiServicesTablePointer)
LoadConstantToReg (FixedPcdGet32(PcdPeiGlobalVariableSize), r1)
sub sp, sp, r1
_PrepareArguments:
# The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector
LoadConstantToReg (FixedPcdGet32(PcdNormalFdBaseAddress), r2) LoadConstantToReg (FixedPcdGet32(PcdNormalFdBaseAddress), r2)
add r2, r2, #4 add r2, r2, #4
ldr r1, [r2] ldr r1, [r2]

24
ArmPlatformPkg/PrePeiCore/PrePeiCoreEntryPoint.asm
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@ -33,15 +33,25 @@ _ModuleEntryPoint
_SetupStack _SetupStack
// Setup Stack for the 4 CPU cores // Setup Stack for the 4 CPU cores
LoadConstantToReg (FixedPcdGet32(PcdCPUCoresNonSecStackBase) ,r1) LoadConstantToReg (FixedPcdGet32(PcdCPUCoresNonSecStackBase), r1)
LoadConstantToReg (FixedPcdGet32(PcdCPUCoresNonSecStackSize) ,r2) LoadConstantToReg (FixedPcdGet32(PcdCPUCoresNonSecStackSize), r2)
mov r3,r0 // r3 = core_id mov r3, r0 // r3 = core_id
mul r3,r3,r2 // r3 = core_id * stack_size = offset from the stack base mul r3, r3, r2 // r3 = core_id * stack_size = offset from the stack base
add r3,r3,r1 // r3 = stack_base + offset add r3, r3, r1 // r3 = stack_base + offset
add r3,r3,r2,LSR #1 // r3 = stack_offset + (stack_size/2) <-- the top half is for the heap add r3, r3, r2, LSR #1 // r3 = stack_offset + (stack_size/2) <-- the top half is for the heap
mov sp, r3 mov sp, r3
// Only allocate memory in top of the primary core stack
cmp r0, #0
bne _PrepareArguments
_AllocateGlobalPeiVariables
// Reserve top of the stack for Global PEI Variables (eg: PeiServicesTablePointer)
LoadConstantToReg (FixedPcdGet32(PcdPeiGlobalVariableSize), r1)
sub sp, sp, r1
_PrepareArguments
// The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector // The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector
LoadConstantToReg (FixedPcdGet32(PcdNormalFdBaseAddress), r2) LoadConstantToReg (FixedPcdGet32(PcdNormalFdBaseAddress), r2)
add r2, r2, #4 add r2, r2, #4

2
ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
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@ -59,5 +59,7 @@
gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase
gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize
gArmPlatformTokenSpaceGuid.PcdPeiGlobalVariableSize
gArmTokenSpaceGuid.PcdGicDistributorBase gArmTokenSpaceGuid.PcdGicDistributorBase
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase

2
ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
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@ -57,5 +57,7 @@
gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase
gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize
gArmPlatformTokenSpaceGuid.PcdPeiGlobalVariableSize
gArmTokenSpaceGuid.PcdGicDistributorBase gArmTokenSpaceGuid.PcdGicDistributorBase
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase