mirror of https://github.com/acidanthera/audk.git
ArmPlatformPkg/PrePeiCore: Reserve some memory on the top of the stack for Global Variables in XIP code
The size of this memory is controlled by a PCD. The Global Variable in this regsion are defined by their offset. This memory region can be use to store the PEI Services Table Pointer. Update the PeiServicesTablePointerLib to use this region instead of PcdPeiServicePtrAddr. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11803 6f19259b-4bc3-4df7-8a09-765794883524
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oliviermartin
parent
936eff09c3
commit
47a8e12fe1
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@ -46,8 +46,6 @@
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# Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.
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gArmPlatformTokenSpaceGuid.PcdMPCoreSupport|0|UINT32|0x00000002
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gArmPlatformTokenSpaceGuid.PcdPeiServicePtrAddr|0|UINT32|0x00000003
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# Stack for CPU Cores in Secure Mode
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gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0|UINT32|0x00000004
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gArmPlatformTokenSpaceGuid.PcdCPUCoreSecStackSize|0|UINT32|0x00000005
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@ -65,6 +63,15 @@
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# Size of the region reserved for fixed address allocations (Reserved 128MB by default)
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gArmPlatformTokenSpaceGuid.PcdSystemMemoryFixRegionSize|0x08000000|UINT32|0x00000014
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# Size to reserve in the primary core stack for PEI Global Variables
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# = sizeof(UINTN) /* PcdPeiServicePtr or HobListPtr */
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gArmPlatformTokenSpaceGuid.PcdPeiGlobalVariableSize|0x4|UINT32|0x00000016
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# PeiServicePtr and HobListPtr shares the same location in the PEI Global Variable list
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# PeiServicePtr is only valid with PEI Core and HobListPtr only when the PEI Core is skipped.
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gArmPlatformTokenSpaceGuid.PcdPeiServicePtrGlobalOffset|0x4|UINT32|0x00000017
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gArmPlatformTokenSpaceGuid.PcdHobListPtrGlobalOffset|0x4|UINT32|0x00000018
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#
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# ARM Primecells
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#
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@ -348,7 +348,6 @@
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# Stack for CPU Cores in Non Secure Mode
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gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase|0x48000000 # Top of SEC Stack for Normal World
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gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize|0x20000 # Size of SEC Stack for Normal World
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gArmPlatformTokenSpaceGuid.PcdPeiServicePtrAddr|0x48020004 # Pei Services Ptr just above stack
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# Non Sec UEFI Firmware: These two PCDs must match PcdFlashFvMainBase/PcdFlashFvMainSize
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gArmTokenSpaceGuid.PcdNormalFdBaseAddress|0x40050000 # Must be equal to gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase
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@ -352,7 +352,6 @@
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# Stacks for MPCores in Normal World
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gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase|0x48000000 # Top of SEC Stack for Normal World
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gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize|0x20000 # Stack for each of the 4 CPU cores
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gArmPlatformTokenSpaceGuid.PcdPeiServicePtrAddr|0x48020004 # Pei Services Ptr just above stack
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# Non Sec UEFI Firmware: These two PCDs must match PcdFlashFvMainBase/PcdFlashFvMainSize
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gArmTokenSpaceGuid.PcdNormalFdBaseAddress|0x40050000 # Must be equal to gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase
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@ -383,7 +383,6 @@
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# Stacks for MPCores in Normal World
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gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase|0x48000000 # Top of SEC Stack for Normal World
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gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize|0x00020000 # Stack for each of the 4 CPU cores
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gArmPlatformTokenSpaceGuid.PcdPeiServicePtrAddr|0x48020004 # pei services ptr just above stack. Overlapped with the stack of CoreId 1
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# System Memory (1GB)
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@ -39,7 +39,7 @@ SetPeiServicesTablePointer (
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UINTN *PeiPtrLoc;
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ASSERT (PeiServicesTablePointer != NULL);
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PeiPtrLoc = (UINTN *)(UINTN)PcdGet32(PcdPeiServicePtrAddr);
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PeiPtrLoc = (UINTN *)(UINTN)(PcdGet32 (PcdCPUCoresNonSecStackBase) + (PcdGet32 (PcdCPUCoresNonSecStackSize) / 2) - PcdGet32 (PcdPeiServicePtrGlobalOffset));
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*PeiPtrLoc = (UINTN)PeiServicesTablePointer;
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}
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@ -63,7 +63,7 @@ GetPeiServicesTablePointer (
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{
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UINTN *PeiPtrLoc;
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PeiPtrLoc = (UINTN *)(UINTN)PcdGet32(PcdPeiServicePtrAddr);
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PeiPtrLoc = (UINTN *)(UINTN)(PcdGet32 (PcdCPUCoresNonSecStackBase) + (PcdGet32 (PcdCPUCoresNonSecStackSize) / 2) - PcdGet32 (PcdPeiServicePtrGlobalOffset));
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return (CONST EFI_PEI_SERVICES **)*PeiPtrLoc;
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}
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@ -40,4 +40,7 @@
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DebugLib
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[Pcd]
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gArmPlatformTokenSpaceGuid.PcdPeiServicePtrAddr
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gArmPlatformTokenSpaceGuid.PcdPeiServicePtrGlobalOffset
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gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase
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gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize
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@ -1,22 +1,21 @@
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//
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// Copyright (c) 2011, ARM Limited. All rights reserved.
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//
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http:#opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#
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// This program and the accompanying materials
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// are licensed and made available under the terms and conditions of the BSD License
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// which accompanies this distribution. The full text of the license may be found at
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// http://opensource.org/licenses/bsd-license.php
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//
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// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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//
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//
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#include <AsmMacroIoLib.h>
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#include <Base.h>
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#include <Library/PcdLib.h>
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#include <AutoGen.h>
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#start of the code section
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.text
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.align 3
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@ -45,9 +44,17 @@ _SetupStack:
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add r3,r3,r2,LSR #1 @ r3 = stack_offset + (stack_size/2) <-- the top half is for the heap
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mov sp, r3
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# lr points to area in reset vector block containing PEI core address. lr needs to
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# be saved from the beginning as the _ModuleEntryPoint could call helper functions
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# that will overwrite 'lr'
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# Only allocate memory in top of the primary core stack
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cmp r0, #0
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bne _PrepareArguments
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_AllocateGlobalPeiVariables:
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# Reserve top of the stack for Global PEI Variables (eg: PeiServicesTablePointer)
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LoadConstantToReg (FixedPcdGet32(PcdPeiGlobalVariableSize), r1)
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sub sp, sp, r1
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_PrepareArguments:
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# The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector
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LoadConstantToReg (FixedPcdGet32(PcdNormalFdBaseAddress), r2)
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add r2, r2, #4
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ldr r1, [r2]
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@ -33,15 +33,25 @@ _ModuleEntryPoint
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_SetupStack
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// Setup Stack for the 4 CPU cores
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LoadConstantToReg (FixedPcdGet32(PcdCPUCoresNonSecStackBase) ,r1)
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LoadConstantToReg (FixedPcdGet32(PcdCPUCoresNonSecStackSize) ,r2)
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LoadConstantToReg (FixedPcdGet32(PcdCPUCoresNonSecStackBase), r1)
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LoadConstantToReg (FixedPcdGet32(PcdCPUCoresNonSecStackSize), r2)
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mov r3,r0 // r3 = core_id
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mul r3,r3,r2 // r3 = core_id * stack_size = offset from the stack base
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add r3,r3,r1 // r3 = stack_base + offset
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add r3,r3,r2,LSR #1 // r3 = stack_offset + (stack_size/2) <-- the top half is for the heap
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mov r3, r0 // r3 = core_id
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mul r3, r3, r2 // r3 = core_id * stack_size = offset from the stack base
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add r3, r3, r1 // r3 = stack_base + offset
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add r3, r3, r2, LSR #1 // r3 = stack_offset + (stack_size/2) <-- the top half is for the heap
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mov sp, r3
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// Only allocate memory in top of the primary core stack
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cmp r0, #0
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bne _PrepareArguments
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_AllocateGlobalPeiVariables
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// Reserve top of the stack for Global PEI Variables (eg: PeiServicesTablePointer)
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LoadConstantToReg (FixedPcdGet32(PcdPeiGlobalVariableSize), r1)
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sub sp, sp, r1
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_PrepareArguments
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// The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector
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LoadConstantToReg (FixedPcdGet32(PcdNormalFdBaseAddress), r2)
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add r2, r2, #4
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@ -59,5 +59,7 @@
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gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase
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gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize
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gArmPlatformTokenSpaceGuid.PcdPeiGlobalVariableSize
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gArmTokenSpaceGuid.PcdGicDistributorBase
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gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
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@ -57,5 +57,7 @@
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gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackBase
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gArmPlatformTokenSpaceGuid.PcdCPUCoresNonSecStackSize
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gArmPlatformTokenSpaceGuid.PcdPeiGlobalVariableSize
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gArmTokenSpaceGuid.PcdGicDistributorBase
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gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
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