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ArmPkg/DebugAgentSymbolsBaseLib: remove exception handling
DebugAgentSymbolsBaseLib is an optional library that is in charge of extracting debug headers from SEC and PEI_CORE images in memory so the filename and the offset in memory can be reported via the UART, allowing a developer to load debugging symbols into his debugger. Interestingly enough, DebugAgentSymbolsBaseLib is also in charge of exception handling before this duty is taken over by either the PEI core, or the CPU DXE driver when running under PrePi. Since exceptions are not actually handled at all on AArch64, and simply routed to the DefaultExceptionHandlerLib (for which a special version has been created to be usable this early), let's get rid of this dubious functionality altogether. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
This commit is contained in:
Ard Biesheuvel
parent
5072c47411
commit
47d9777331
@ -1,96 +0,0 @@
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#------------------------------------------------------------------------------
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#
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# Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#------------------------------------------------------------------------------
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#include <Chipset/AArch64.h>
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GCC_ASM_IMPORT(DefaultExceptionHandler)
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.text
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VECTOR_BASE(DebugAgentVectorTable)
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//
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// Current EL with SP0 : 0x0 - 0x180
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//
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VECTOR_ENTRY(DebugAgentVectorTable, ARM_VECTOR_CUR_SP0_SYNC)
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ASM_PFX(SynchronousExceptionSP0):
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b ASM_PFX(SynchronousExceptionSP0)
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VECTOR_ENTRY(DebugAgentVectorTable, ARM_VECTOR_CUR_SP0_IRQ)
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ASM_PFX(IrqSP0):
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b ASM_PFX(IrqSP0)
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VECTOR_ENTRY(DebugAgentVectorTable, ARM_VECTOR_CUR_SP0_FIQ)
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ASM_PFX(FiqSP0):
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b ASM_PFX(FiqSP0)
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VECTOR_ENTRY(DebugAgentVectorTable, ARM_VECTOR_CUR_SP0_SERR)
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ASM_PFX(SErrorSP0):
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b ASM_PFX(SErrorSP0)
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//
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// Current EL with SPx: 0x200 - 0x380
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//
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VECTOR_ENTRY(DebugAgentVectorTable, ARM_VECTOR_CUR_SPx_SYNC)
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ASM_PFX(SynchronousExceptionSPx):
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b ASM_PFX(SynchronousExceptionSPx)
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VECTOR_ENTRY(DebugAgentVectorTable, ARM_VECTOR_CUR_SPx_IRQ)
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ASM_PFX(IrqSPx):
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b ASM_PFX(IrqSPx)
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VECTOR_ENTRY(DebugAgentVectorTable, ARM_VECTOR_CUR_SPx_FIQ)
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ASM_PFX(FiqSPx):
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b ASM_PFX(FiqSPx)
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VECTOR_ENTRY(DebugAgentVectorTable, ARM_VECTOR_CUR_SPx_SERR)
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ASM_PFX(SErrorSPx):
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b ASM_PFX(SErrorSPx)
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/* Lower EL using AArch64 : 0x400 - 0x580 */
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VECTOR_ENTRY(DebugAgentVectorTable, ARM_VECTOR_LOW_A64_SYNC)
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ASM_PFX(SynchronousExceptionA64):
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b ASM_PFX(SynchronousExceptionA64)
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VECTOR_ENTRY(DebugAgentVectorTable, ARM_VECTOR_LOW_A64_IRQ)
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ASM_PFX(IrqA64):
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b ASM_PFX(IrqA64)
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VECTOR_ENTRY(DebugAgentVectorTable, ARM_VECTOR_LOW_A64_FIQ)
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ASM_PFX(FiqA64):
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b ASM_PFX(FiqA64)
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VECTOR_ENTRY(DebugAgentVectorTable, ARM_VECTOR_LOW_A64_SERR)
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ASM_PFX(SErrorA64):
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b ASM_PFX(SErrorA64)
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//
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// Lower EL using AArch32 : 0x600 - 0x780
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//
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VECTOR_ENTRY(DebugAgentVectorTable, ARM_VECTOR_LOW_A32_SYNC)
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ASM_PFX(SynchronousExceptionA32):
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b ASM_PFX(SynchronousExceptionA32)
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VECTOR_ENTRY(DebugAgentVectorTable, ARM_VECTOR_LOW_A32_IRQ)
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ASM_PFX(IrqA32):
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b ASM_PFX(IrqA32)
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VECTOR_ENTRY(DebugAgentVectorTable, ARM_VECTOR_LOW_A32_FIQ)
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ASM_PFX(FiqA32):
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b ASM_PFX(FiqA32)
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VECTOR_ENTRY(DebugAgentVectorTable, ARM_VECTOR_LOW_A32_SERR)
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ASM_PFX(SErrorA32):
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b ASM_PFX(SErrorA32)
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VECTOR_END(DebugAgentVectorTable)
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@ -1,277 +0,0 @@
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#------------------------------------------------------------------------------
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#
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# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
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# Copyright (c) 2011 - 2012, ARM Ltd. All rights reserved.<BR>
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#------------------------------------------------------------------------------
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#include <Library/PcdLib.h>
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/*
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This is the stack constructed by the exception handler (low address to high address)
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# R0 - IFAR is EFI_SYSTEM_CONTEXT for ARM
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Reg Offset
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=== ======
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R0 0x00 # stmfd SP!,{R0-R12}
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R1 0x04
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R2 0x08
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R3 0x0c
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R4 0x10
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R5 0x14
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R6 0x18
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R7 0x1c
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R8 0x20
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R9 0x24
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R10 0x28
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R11 0x2c
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R12 0x30
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SP 0x34 # reserved via adding 0x20 (32) to the SP
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LR 0x38
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PC 0x3c
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CPSR 0x40
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DFSR 0x44
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DFAR 0x48
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IFSR 0x4c
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IFAR 0x50
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LR 0x54 # SVC Link register (we need to restore it)
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LR 0x58 # pushed by srsfd
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CPSR 0x5c
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*/
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GCC_ASM_EXPORT(DebugAgentVectorTable)
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GCC_ASM_IMPORT(DefaultExceptionHandler)
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.text
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.syntax unified
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#if !defined(__APPLE__)
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.fpu neon @ makes vpush/vpop assemble
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#endif
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.align 5
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//
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// This code gets copied to the ARM vector table
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// ExceptionHandlersStart - ExceptionHandlersEnd gets copied
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//
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ASM_PFX(DebugAgentVectorTable):
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b ASM_PFX(ResetEntry)
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b ASM_PFX(UndefinedInstructionEntry)
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b ASM_PFX(SoftwareInterruptEntry)
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b ASM_PFX(PrefetchAbortEntry)
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b ASM_PFX(DataAbortEntry)
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b ASM_PFX(ReservedExceptionEntry)
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b ASM_PFX(IrqEntry)
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b ASM_PFX(FiqEntry)
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ASM_PFX(ResetEntry):
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srsdb #0x13! @ Store return state on SVC stack
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@ We are already in SVC mode
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stmfd SP!,{LR} @ Store the link register for the current mode
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sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
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stmfd SP!,{R0-R12} @ Store the register state
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mov R0,#0 @ ExceptionType
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ldr R1,ASM_PFX(CommonExceptionEntry)
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bx R1
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ASM_PFX(UndefinedInstructionEntry):
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sub LR, LR, #4 @ Only -2 for Thumb, adjust in CommonExceptionEntry
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srsdb #0x13! @ Store return state on SVC stack
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cps #0x13 @ Switch to SVC for common stack
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stmfd SP!,{LR} @ Store the link register for the current mode
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sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
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stmfd SP!,{R0-R12} @ Store the register state
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mov R0,#1 @ ExceptionType
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ldr R1,ASM_PFX(CommonExceptionEntry)
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bx R1
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ASM_PFX(SoftwareInterruptEntry):
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sub LR, LR, #4 @ Only -2 for Thumb, adjust in CommonExceptionEntry
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srsdb #0x13! @ Store return state on SVC stack
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@ We are already in SVC mode
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stmfd SP!,{LR} @ Store the link register for the current mode
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sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
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stmfd SP!,{R0-R12} @ Store the register state
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mov R0,#2 @ ExceptionType
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ldr R1,ASM_PFX(CommonExceptionEntry)
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bx R1
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ASM_PFX(PrefetchAbortEntry):
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sub LR,LR,#4
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srsdb #0x13! @ Store return state on SVC stack
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cps #0x13 @ Switch to SVC for common stack
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stmfd SP!,{LR} @ Store the link register for the current mode
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sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
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stmfd SP!,{R0-R12} @ Store the register state
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mov R0,#3 @ ExceptionType
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ldr R1,ASM_PFX(CommonExceptionEntry)
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bx R1
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ASM_PFX(DataAbortEntry):
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sub LR,LR,#8
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srsdb #0x13! @ Store return state on SVC stack
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cps #0x13 @ Switch to SVC for common stack
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stmfd SP!,{LR} @ Store the link register for the current mode
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sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
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stmfd SP!,{R0-R12} @ Store the register state
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mov R0,#4
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ldr R1,ASM_PFX(CommonExceptionEntry)
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bx R1
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ASM_PFX(ReservedExceptionEntry):
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srsdb #0x13! @ Store return state on SVC stack
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cps #0x13 @ Switch to SVC for common stack
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stmfd SP!,{LR} @ Store the link register for the current mode
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sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
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stmfd SP!,{R0-R12} @ Store the register state
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mov R0,#5
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ldr R1,ASM_PFX(CommonExceptionEntry)
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bx R1
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ASM_PFX(IrqEntry):
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sub LR,LR,#4
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srsdb #0x13! @ Store return state on SVC stack
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cps #0x13 @ Switch to SVC for common stack
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stmfd SP!,{LR} @ Store the link register for the current mode
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sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
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stmfd SP!,{R0-R12} @ Store the register state
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mov R0,#6 @ ExceptionType
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ldr R1,ASM_PFX(CommonExceptionEntry)
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bx R1
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ASM_PFX(FiqEntry):
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sub LR,LR,#4
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srsdb #0x13! @ Store return state on SVC stack
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cps #0x13 @ Switch to SVC for common stack
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stmfd SP!,{LR} @ Store the link register for the current mode
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sub SP,SP,#0x20 @ Save space for SP, LR, PC, IFAR - CPSR
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stmfd SP!,{R0-R12} @ Store the register state
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@ Since we have already switch to SVC R8_fiq - R12_fiq
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@ never get used or saved
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mov R0,#7 @ ExceptionType
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ldr R1,ASM_PFX(CommonExceptionEntry)
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bx R1
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//
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// This gets patched by the C code that patches in the vector table
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//
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ASM_PFX(CommonExceptionEntry):
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.word ASM_PFX(AsmCommonExceptionEntry)
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ASM_PFX(ExceptionHandlersEnd):
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//
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// This code runs from CpuDxe driver loaded address. It is patched into
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// CommonExceptionEntry.
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//
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ASM_PFX(AsmCommonExceptionEntry):
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mrc p15, 0, R1, c6, c0, 2 @ Read IFAR
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str R1, [SP, #0x50] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFAR
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mrc p15, 0, R1, c5, c0, 1 @ Read IFSR
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str R1, [SP, #0x4c] @ Store it in EFI_SYSTEM_CONTEXT_ARM.IFSR
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mrc p15, 0, R1, c6, c0, 0 @ Read DFAR
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str R1, [SP, #0x48] @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFAR
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mrc p15, 0, R1, c5, c0, 0 @ Read DFSR
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str R1, [SP, #0x44] @ Store it in EFI_SYSTEM_CONTEXT_ARM.DFSR
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ldr R1, [SP, #0x5c] @ srsdb saved pre-exception CPSR on the stack
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str R1, [SP, #0x40] @ Store it in EFI_SYSTEM_CONTEXT_ARM.CPSR
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add R2, SP, #0x38 @ Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR
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and R3, R1, #0x1f @ Check CPSR to see if User or System Mode
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cmp R3, #0x1f @ if ((CPSR == 0x10) || (CPSR == 0x1df))
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cmpne R3, #0x10 @
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stmdaeq R2, {lr}^ @ save unbanked lr
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@ else
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stmdane R2, {lr} @ save SVC lr
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ldr R5, [SP, #0x58] @ PC is the LR pushed by srsfd
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@ Check to see if we have to adjust for Thumb entry
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sub r4, r0, #1 @ if (ExceptionType == 1 || ExceptionType ==2)) {
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cmp r4, #1 @ // UND & SVC have different LR adjust for Thumb
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bhi NoAdjustNeeded
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tst r1, #0x20 @ if ((CPSR & T)) == T) { // Thumb Mode on entry
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addne R5, R5, #2 @ PC += 2@
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str R5,[SP,#0x58] @ Update LR value pused by srsfd
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NoAdjustNeeded:
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str R5, [SP, #0x3c] @ Store it in EFI_SYSTEM_CONTEXT_ARM.PC
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sub R1, SP, #0x60 @ We pused 0x60 bytes on the stack
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str R1, [SP, #0x34] @ Store it in EFI_SYSTEM_CONTEXT_ARM.SP
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@ R0 is ExceptionType
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mov R1,SP @ R1 is SystemContext
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#if (FixedPcdGet32(PcdVFPEnabled))
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vpush {d0-d15} @ save vstm registers in case they are used in optimizations
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#endif
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/*
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VOID
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EFIAPI
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DefaultExceptionHandler (
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IN EFI_EXCEPTION_TYPE ExceptionType, R0
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IN OUT EFI_SYSTEM_CONTEXT SystemContext R1
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)
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*/
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blx ASM_PFX(DefaultExceptionHandler) @ Call exception handler
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#if (FixedPcdGet32(PcdVFPEnabled))
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vpop {d0-d15}
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#endif
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ldr R1, [SP, #0x4c] @ Restore EFI_SYSTEM_CONTEXT_ARM.IFSR
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mcr p15, 0, R1, c5, c0, 1 @ Write IFSR
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ldr R1, [SP, #0x44] @ sRestore EFI_SYSTEM_CONTEXT_ARM.DFSR
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mcr p15, 0, R1, c5, c0, 0 @ Write DFSR
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ldr R1,[SP,#0x3c] @ EFI_SYSTEM_CONTEXT_ARM.PC
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str R1,[SP,#0x58] @ Store it back to srsfd stack slot so it can be restored
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ldr R1,[SP,#0x40] @ EFI_SYSTEM_CONTEXT_ARM.CPSR
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str R1,[SP,#0x5c] @ Store it back to srsfd stack slot so it can be restored
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add R3, SP, #0x54 @ Make R3 point to SVC LR saved on entry
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add R2, SP, #0x38 @ Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR
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and R1, R1, #0x1f @ Check to see if User or System Mode
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cmp R1, #0x1f @ if ((CPSR == 0x10) || (CPSR == 0x1f))
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cmpne R1, #0x10 @
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ldmibeq R2, {lr}^ @ restore unbanked lr
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@ else
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ldmibne R3, {lr} @ restore SVC lr, via ldmfd SP!, {LR}
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ldmfd SP!,{R0-R12} @ Restore general purpose registers
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@ Exception handler can not change SP
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add SP,SP,#0x20 @ Clear out the remaining stack space
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ldmfd SP!,{LR} @ restore the link register for this context
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rfefd SP! @ return from exception via srsfd stack slot
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@ -1,273 +0,0 @@
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//------------------------------------------------------------------------------
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//
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// Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
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// Copyright (c) 2011 - 2012, ARM Ltd. All rights reserved.<BR>
|
||||
//
|
||||
// This program and the accompanying materials
|
||||
// are licensed and made available under the terms and conditions of the BSD License
|
||||
// which accompanies this distribution. The full text of the license may be found at
|
||||
// http://opensource.org/licenses/bsd-license.php
|
||||
//
|
||||
// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
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//
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//------------------------------------------------------------------------------
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#include <Library/PcdLib.h>
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/*
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This is the stack constructed by the exception handler (low address to high address)
|
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# R0 - IFAR is EFI_SYSTEM_CONTEXT for ARM
|
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Reg Offset
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=== ======
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R0 0x00 # stmfd SP!,{R0-R12}
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R1 0x04
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R2 0x08
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R3 0x0c
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R4 0x10
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R5 0x14
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R6 0x18
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R7 0x1c
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R8 0x20
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R9 0x24
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R10 0x28
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R11 0x2c
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R12 0x30
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SP 0x34 # reserved via adding 0x20 (32) to the SP
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LR 0x38
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PC 0x3c
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CPSR 0x40
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DFSR 0x44
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DFAR 0x48
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IFSR 0x4c
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IFAR 0x50
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LR 0x54 # SVC Link register (we need to restore it)
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LR 0x58 # pushed by srsfd
|
||||
CPSR 0x5c
|
||||
|
||||
*/
|
||||
|
||||
EXPORT DebugAgentVectorTable
|
||||
IMPORT DefaultExceptionHandler
|
||||
|
||||
PRESERVE8
|
||||
AREA DebugAgentException, CODE, READONLY, CODEALIGN, ALIGN=5
|
||||
|
||||
//
|
||||
// This code gets copied to the ARM vector table
|
||||
// ExceptionHandlersStart - ExceptionHandlersEnd gets copied
|
||||
//
|
||||
DebugAgentVectorTable FUNCTION
|
||||
b ResetEntry
|
||||
b UndefinedInstructionEntry
|
||||
b SoftwareInterruptEntry
|
||||
b PrefetchAbortEntry
|
||||
b DataAbortEntry
|
||||
b ReservedExceptionEntry
|
||||
b IrqEntry
|
||||
b FiqEntry
|
||||
ENDFUNC
|
||||
|
||||
ResetEntry
|
||||
srsfd #0x13! ; Store return state on SVC stack
|
||||
; We are already in SVC mode
|
||||
stmfd SP!,{LR} ; Store the link register for the current mode
|
||||
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR
|
||||
stmfd SP!,{R0-R12} ; Store the register state
|
||||
|
||||
mov R0,#0 ; ExceptionType
|
||||
ldr R1,CommonExceptionEntry
|
||||
bx R1
|
||||
|
||||
UndefinedInstructionEntry
|
||||
sub LR, LR, #4 ; Only -2 for Thumb, adjust in CommonExceptionEntry
|
||||
srsfd #0x13! ; Store return state on SVC stack
|
||||
cps #0x13 ; Switch to SVC for common stack
|
||||
stmfd SP!,{LR} ; Store the link register for the current mode
|
||||
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR
|
||||
stmfd SP!,{R0-R12} ; Store the register state
|
||||
|
||||
mov R0,#1 ; ExceptionType
|
||||
ldr R1,CommonExceptionEntry;
|
||||
bx R1
|
||||
|
||||
SoftwareInterruptEntry
|
||||
sub LR, LR, #4 ; Only -2 for Thumb, adjust in CommonExceptionEntry
|
||||
srsfd #0x13! ; Store return state on SVC stack
|
||||
; We are already in SVC mode
|
||||
stmfd SP!,{LR} ; Store the link register for the current mode
|
||||
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR
|
||||
stmfd SP!,{R0-R12} ; Store the register state
|
||||
|
||||
mov R0,#2 ; ExceptionType
|
||||
ldr R1,CommonExceptionEntry
|
||||
bx R1
|
||||
|
||||
PrefetchAbortEntry
|
||||
sub LR,LR,#4
|
||||
srsfd #0x13! ; Store return state on SVC stack
|
||||
cps #0x13 ; Switch to SVC for common stack
|
||||
stmfd SP!,{LR} ; Store the link register for the current mode
|
||||
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR
|
||||
stmfd SP!,{R0-R12} ; Store the register state
|
||||
|
||||
mov R0,#3 ; ExceptionType
|
||||
ldr R1,CommonExceptionEntry
|
||||
bx R1
|
||||
|
||||
DataAbortEntry
|
||||
sub LR,LR,#8
|
||||
srsfd #0x13! ; Store return state on SVC stack
|
||||
cps #0x13 ; Switch to SVC for common stack
|
||||
stmfd SP!,{LR} ; Store the link register for the current mode
|
||||
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR
|
||||
stmfd SP!,{R0-R12} ; Store the register state
|
||||
|
||||
mov R0,#4 ; ExceptionType
|
||||
ldr R1,CommonExceptionEntry
|
||||
bx R1
|
||||
|
||||
ReservedExceptionEntry
|
||||
srsfd #0x13! ; Store return state on SVC stack
|
||||
cps #0x13 ; Switch to SVC for common stack
|
||||
stmfd SP!,{LR} ; Store the link register for the current mode
|
||||
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR
|
||||
stmfd SP!,{R0-R12} ; Store the register state
|
||||
|
||||
mov R0,#5 ; ExceptionType
|
||||
ldr R1,CommonExceptionEntry
|
||||
bx R1
|
||||
|
||||
IrqEntry
|
||||
sub LR,LR,#4
|
||||
srsfd #0x13! ; Store return state on SVC stack
|
||||
cps #0x13 ; Switch to SVC for common stack
|
||||
stmfd SP!,{LR} ; Store the link register for the current mode
|
||||
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR
|
||||
stmfd SP!,{R0-R12} ; Store the register state
|
||||
|
||||
mov R0,#6 ; ExceptionType
|
||||
ldr R1,CommonExceptionEntry
|
||||
bx R1
|
||||
|
||||
FiqEntry
|
||||
sub LR,LR,#4
|
||||
srsfd #0x13! ; Store return state on SVC stack
|
||||
cps #0x13 ; Switch to SVC for common stack
|
||||
stmfd SP!,{LR} ; Store the link register for the current mode
|
||||
sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR
|
||||
stmfd SP!,{R0-R12} ; Store the register state
|
||||
; Since we have already switch to SVC R8_fiq - R12_fiq
|
||||
; never get used or saved
|
||||
mov R0,#7 ; ExceptionType
|
||||
ldr R1,CommonExceptionEntry
|
||||
bx R1
|
||||
|
||||
//
|
||||
// This gets patched by the C code that patches in the vector table
|
||||
//
|
||||
CommonExceptionEntry
|
||||
dcd AsmCommonExceptionEntry
|
||||
|
||||
ExceptionHandlersEnd
|
||||
|
||||
//
|
||||
// This code runs from CpuDxe driver loaded address. It is patched into
|
||||
// CommonExceptionEntry.
|
||||
//
|
||||
AsmCommonExceptionEntry
|
||||
mrc p15, 0, R1, c6, c0, 2 ; Read IFAR
|
||||
str R1, [SP, #0x50] ; Store it in EFI_SYSTEM_CONTEXT_ARM.IFAR
|
||||
|
||||
mrc p15, 0, R1, c5, c0, 1 ; Read IFSR
|
||||
str R1, [SP, #0x4c] ; Store it in EFI_SYSTEM_CONTEXT_ARM.IFSR
|
||||
|
||||
mrc p15, 0, R1, c6, c0, 0 ; Read DFAR
|
||||
str R1, [SP, #0x48] ; Store it in EFI_SYSTEM_CONTEXT_ARM.DFAR
|
||||
|
||||
mrc p15, 0, R1, c5, c0, 0 ; Read DFSR
|
||||
str R1, [SP, #0x44] ; Store it in EFI_SYSTEM_CONTEXT_ARM.DFSR
|
||||
|
||||
ldr R1, [SP, #0x5c] ; srsfd saved pre-exception CPSR on the stack
|
||||
str R1, [SP, #0x40] ; Store it in EFI_SYSTEM_CONTEXT_ARM.CPSR
|
||||
|
||||
add R2, SP, #0x38 ; Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR
|
||||
and R3, R1, #0x1f ; Check CPSR to see if User or System Mode
|
||||
cmp R3, #0x1f ; if ((CPSR == 0x10) || (CPSR == 0x1df))
|
||||
cmpne R3, #0x10 ;
|
||||
stmeqed R2, {lr}^ ; save unbanked lr
|
||||
; else
|
||||
stmneed R2, {lr} ; save SVC lr
|
||||
|
||||
|
||||
ldr R5, [SP, #0x58] ; PC is the LR pushed by srsfd
|
||||
; Check to see if we have to adjust for Thumb entry
|
||||
sub r4, r0, #1 ; if (ExceptionType == 1 || ExceptionType ==2)) {
|
||||
cmp r4, #1 ; // UND & SVC have different LR adjust for Thumb
|
||||
bhi NoAdjustNeeded
|
||||
|
||||
tst r1, #0x20 ; if ((CPSR & T)) == T) { // Thumb Mode on entry
|
||||
addne R5, R5, #2 ; PC += 2;
|
||||
str R5,[SP,#0x58] ; Update LR value pused by srsfd
|
||||
|
||||
NoAdjustNeeded
|
||||
|
||||
str R5, [SP, #0x3c] ; Store it in EFI_SYSTEM_CONTEXT_ARM.PC
|
||||
|
||||
sub R1, SP, #0x60 ; We pused 0x60 bytes on the stack
|
||||
str R1, [SP, #0x34] ; Store it in EFI_SYSTEM_CONTEXT_ARM.SP
|
||||
|
||||
; R0 is ExceptionType
|
||||
mov R1,SP ; R1 is SystemContext
|
||||
|
||||
#if (FixedPcdGet32(PcdVFPEnabled))
|
||||
vpush {d0-d15} ; save vstm registers in case they are used in optimizations
|
||||
#endif
|
||||
|
||||
/*
|
||||
VOID
|
||||
EFIAPI
|
||||
DefaultExceptionHandler (
|
||||
IN EFI_EXCEPTION_TYPE ExceptionType, R0
|
||||
IN OUT EFI_SYSTEM_CONTEXT SystemContext R1
|
||||
)
|
||||
|
||||
*/
|
||||
blx DefaultExceptionHandler ; Call exception handler
|
||||
|
||||
#if (FixedPcdGet32(PcdVFPEnabled))
|
||||
vpop {d0-d15}
|
||||
#endif
|
||||
|
||||
ldr R1, [SP, #0x4c] ; Restore EFI_SYSTEM_CONTEXT_ARM.IFSR
|
||||
mcr p15, 0, R1, c5, c0, 1 ; Write IFSR
|
||||
|
||||
ldr R1, [SP, #0x44] ; sRestore EFI_SYSTEM_CONTEXT_ARM.DFSR
|
||||
mcr p15, 0, R1, c5, c0, 0 ; Write DFSR
|
||||
|
||||
ldr R1,[SP,#0x3c] ; EFI_SYSTEM_CONTEXT_ARM.PC
|
||||
str R1,[SP,#0x58] ; Store it back to srsfd stack slot so it can be restored
|
||||
|
||||
ldr R1,[SP,#0x40] ; EFI_SYSTEM_CONTEXT_ARM.CPSR
|
||||
str R1,[SP,#0x5c] ; Store it back to srsfd stack slot so it can be restored
|
||||
|
||||
add R3, SP, #0x54 ; Make R3 point to SVC LR saved on entry
|
||||
add R2, SP, #0x38 ; Make R2 point to EFI_SYSTEM_CONTEXT_ARM.LR
|
||||
and R1, R1, #0x1f ; Check to see if User or System Mode
|
||||
cmp R1, #0x1f ; if ((CPSR == 0x10) || (CPSR == 0x1f))
|
||||
cmpne R1, #0x10 ;
|
||||
ldmeqed R2, {lr}^ ; restore unbanked lr
|
||||
; else
|
||||
ldmneed R3, {lr} ; restore SVC lr, via ldmfd SP!, {LR}
|
||||
|
||||
ldmfd SP!,{R0-R12} ; Restore general purpose registers
|
||||
; Exception handler can not change SP
|
||||
|
||||
add SP,SP,#0x20 ; Clear out the remaining stack space
|
||||
ldmfd SP!,{LR} ; restore the link register for this context
|
||||
rfefd SP! ; return from exception via srsfd stack slot
|
||||
|
||||
END
|
||||
@ -14,7 +14,6 @@
|
||||
**/
|
||||
|
||||
#include <Uefi.h>
|
||||
#include <Library/ArmLib.h>
|
||||
#include <Library/BaseLib.h>
|
||||
#include <Library/BaseMemoryLib.h>
|
||||
#include <Library/DebugLib.h>
|
||||
@ -283,12 +282,6 @@ InitializeDebugAgent (
|
||||
EFI_FFS_FILE_HEADER *FfsHeader;
|
||||
PE_COFF_LOADER_IMAGE_CONTEXT ImageContext;
|
||||
|
||||
// Now we've got UART, check the Debug Agent Vector Table
|
||||
// Note: The AArch64 Vector table must be 2k-byte aligned - if this assertion fails ensure
|
||||
// 'Align=4K' is defined into your FDF for this module.
|
||||
ASSERT (((UINTN)DebugAgentVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);
|
||||
ArmWriteVBar ((UINTN)DebugAgentVectorTable);
|
||||
|
||||
// We use InitFlag to know if DebugAgent has been initialized from
|
||||
// Sec (DEBUG_AGENT_INIT_PREMEM_SEC) or PrePi (DEBUG_AGENT_INIT_POSTMEM_SEC)
|
||||
// modules
|
||||
|
||||
@ -22,22 +22,13 @@
|
||||
[Sources.common]
|
||||
DebugAgentSymbolsBaseLib.c
|
||||
|
||||
[Sources.ARM]
|
||||
Arm/DebugAgentException.asm | RVCT
|
||||
Arm/DebugAgentException.S | GCC
|
||||
|
||||
[Sources.AARCH64]
|
||||
AArch64/DebugAgentException.S
|
||||
|
||||
[Packages]
|
||||
MdePkg/MdePkg.dec
|
||||
MdeModulePkg/MdeModulePkg.dec
|
||||
ArmPkg/ArmPkg.dec
|
||||
|
||||
[LibraryClasses]
|
||||
ArmLib
|
||||
DebugLib
|
||||
DefaultExceptionHandlerLib
|
||||
PcdLib
|
||||
PeCoffExtraActionLib
|
||||
PeCoffLib
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user