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ArmPlatformPkg: detect correct pl011 fifo depth 

pl011 releases earlier than r1p5 has a fifo depth of 16 bytes, whereas
version r1p5 upwards has a fifo depth of 32 bytes. The pl011 driver was
hardwired to 32 byte depth, causing dropped characters on some platforms
(including default settings on FVP Base and Foundation models).
Update driver to select 16 or 32 on port initialization by checking the
component revision.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16656 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Leif Lindholm 2015-01-23 16:10:00 +00:00 committed by oliviermartin
parent ac83357a43
commit 48edf6be7f
2 changed files with 13 additions and 2 deletions
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7
ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.c
View File

@ -50,12 +50,15 @@ PL011UartInitializePort (
LineControl = 0;
// The PL011 supports a buffer of either 1 or 32 chars. Therefore we can accept
// The PL011 supports a buffer of 1, 16 or 32 chars. Therefore we can accept
// 1 char buffer as the minimum fifo size. Because everything can be rounded down,
// there is no maximum fifo size.
if ((*ReceiveFifoDepth == 0) || (*ReceiveFifoDepth >= 32)) {
LineControl |= PL011_UARTLCR_H_FEN;
*ReceiveFifoDepth = 32;
if (PL011_UARTPID2_VER (MmioRead32 (UartBase + UARTPID2)) > PL011_VER_R1P4)
*ReceiveFifoDepth = 32;
else
*ReceiveFifoDepth = 16;
} else {
ASSERT (*ReceiveFifoDepth < 32);
// Nothing else to do. 1 byte fifo is default.

8
ArmPlatformPkg/Include/Drivers/PL011Uart.h
View File

@ -35,6 +35,11 @@
#define UARTICR 0x044
#define UARTDMACR 0x048
#define UARTPID0 0xFE0
#define UARTPID1 0xFE4
#define UARTPID2 0xFE8
#define UARTPID3 0xFEC
// Data status bits
#define UART_DATA_ERROR_MASK 0x0F00
@ -81,6 +86,9 @@
#define PL011_UARTLCR_H_PEN (1 << 1) // Parity Enable
#define PL011_UARTLCR_H_BRK (1 << 0) // Send break
#define PL011_UARTPID2_VER(X) (((X) >> 4) & 0xF)
#define PL011_VER_R1P4 0x2
/*
Programmed hardware of Serial port.