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ArmPkg/CpuDxe/AArch64: Fixed SyncCacheConfig() when first entry is in 3-level 

If the first entry of the memory map is in the third level (case when the region
at 0x0 is smaller than 4KB) then its descriptor type would be TT_TYPE_BLOCK_ENTRY_LEVEL3
(=0x3) which has the same value as TT_TYPE_TABLE_ENTRY (=0x3).
The first condition in GetFirstPageAttribute() needed the table level
to not mix these two descriptor types.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15526 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Olivier Martin 2014-05-14 05:32:07 +00:00 committed by oliviermartin
parent 7da62bc02d
commit 48ef4e4276
1 changed files with 1 additions and 2 deletions
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3
ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c
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@ -32,9 +32,8 @@ GetFirstPageAttribute (
// Get the first entry of the table // Get the first entry of the table
FirstEntry = *FirstLevelTableAddress; FirstEntry = *FirstLevelTableAddress;
if ((FirstEntry & TT_TYPE_MASK) == TT_TYPE_TABLE_ENTRY) { if ((TableLevel != 3) && (FirstEntry & TT_TYPE_MASK) == TT_TYPE_TABLE_ENTRY) {
// Only valid for Levels 0, 1 and 2 // Only valid for Levels 0, 1 and 2
ASSERT (TableLevel < 3);
// Get the attribute of the subsequent table // Get the attribute of the subsequent table
return GetFirstPageAttribute ((UINT64*)(FirstEntry & TT_ADDRESS_MASK_DESCRIPTION_TABLE), TableLevel + 1); return GetFirstPageAttribute ((UINT64*)(FirstEntry & TT_ADDRESS_MASK_DESCRIPTION_TABLE), TableLevel + 1);