mirror of https://github.com/acidanthera/audk.git
OvmfPkg/PciHostBridgeLib: Scan for root bridges when running over Xen
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Gary Lin <glin@suse.com>
This commit is contained in:
Ruiyu Ni
parent
c0a2591b30
commit
49effaf26e
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@ -0,0 +1,75 @@
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/** @file
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Header file of OVMF instance of PciHostBridgeLib.
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Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials are licensed and made available
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under the terms and conditions of the BSD License which accompanies this
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distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php.
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
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WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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PCI_ROOT_BRIDGE *
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ScanForRootBridges (
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UINTN *NumberOfRootBridges
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);
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/**
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Initialize a PCI_ROOT_BRIDGE structure.
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@param[in] Supports Supported attributes.
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@param[in] Attributes Initial attributes.
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@param[in] AllocAttributes Allocation attributes.
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@param[in] RootBusNumber The bus number to store in RootBus.
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@param[in] MaxSubBusNumber The inclusive maximum bus number that can be
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assigned to any subordinate bus found behind any
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PCI bridge hanging off this root bus.
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The caller is repsonsible for ensuring that
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RootBusNumber <= MaxSubBusNumber. If
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RootBusNumber equals MaxSubBusNumber, then the
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root bus has no room for subordinate buses.
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@param[in] Io IO aperture.
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@param[in] Mem MMIO aperture.
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@param[in] MemAbove4G MMIO aperture above 4G.
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@param[in] PMem Prefetchable MMIO aperture.
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@param[in] PMemAbove4G Prefetchable MMIO aperture above 4G.
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@param[out] RootBus The PCI_ROOT_BRIDGE structure (allocated by the
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caller) that should be filled in by this
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function.
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@retval EFI_SUCCESS Initialization successful. A device path
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consisting of an ACPI device path node, with
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UID = RootBusNumber, has been allocated and
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linked into RootBus.
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@retval EFI_OUT_OF_RESOURCES Memory allocation failed.
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**/
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EFI_STATUS
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InitRootBridge (
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IN UINT64 Supports,
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IN UINT64 Attributes,
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IN UINT64 AllocAttributes,
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IN UINT8 RootBusNumber,
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IN UINT8 MaxSubBusNumber,
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IN PCI_ROOT_BRIDGE_APERTURE *Io,
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IN PCI_ROOT_BRIDGE_APERTURE *Mem,
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IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G,
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IN PCI_ROOT_BRIDGE_APERTURE *PMem,
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IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G,
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OUT PCI_ROOT_BRIDGE *RootBus
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);
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@ -28,6 +28,7 @@
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#include <Library/PciHostBridgeLib.h>
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#include <Library/PciLib.h>
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#include <Library/QemuFwCfgLib.h>
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#include "PciHostBridge.h"
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#pragma pack(1)
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@ -113,7 +114,6 @@ STATIC PCI_ROOT_BRIDGE_APERTURE mNonExistAperture = { MAX_UINT64, 0 };
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@retval EFI_OUT_OF_RESOURCES Memory allocation failed.
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**/
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STATIC
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EFI_STATUS
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InitRootBridge (
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IN UINT64 Supports,
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@ -217,6 +217,10 @@ PciHostBridgeGetRootBridges (
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PCI_ROOT_BRIDGE_APERTURE Mem;
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PCI_ROOT_BRIDGE_APERTURE MemAbove4G;
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if (PcdGetBool (PcdPciDisableBusEnumeration)) {
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return ScanForRootBridges (Count);
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}
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Attributes = EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO |
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EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO |
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EFI_PCI_ATTRIBUTE_ISA_IO_16 |
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@ -32,6 +32,8 @@
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[Sources]
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PciHostBridgeLib.c
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XenSupport.c
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PciHostBridge.h
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[Packages]
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MdeModulePkg/MdeModulePkg.dec
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@ -54,3 +56,4 @@
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gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Base
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gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Size
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gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId
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gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration
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@ -0,0 +1,456 @@
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/** @file
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Scan the entire PCI bus for root bridges to support OVMF above Xen.
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Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials are licensed and made available
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under the terms and conditions of the BSD License which accompanies this
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distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php.
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
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WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <PiDxe.h>
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#include <IndustryStandard/Pci.h>
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#include <IndustryStandard/Q35MchIch9.h>
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#include <Protocol/PciHostBridgeResourceAllocation.h>
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#include <Protocol/PciRootBridgeIo.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/DebugLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/PciHostBridgeLib.h>
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#include <Library/PciLib.h>
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#include "PciHostBridge.h"
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STATIC
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VOID
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PcatPciRootBridgeBarExisted (
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IN UINT64 Address,
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OUT UINT32 *OriginalValue,
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OUT UINT32 *Value
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)
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{
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//
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// Preserve the original value
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//
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*OriginalValue = PciRead32 (Address);
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//
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// Disable timer interrupt while the BAR is probed
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//
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DisableInterrupts ();
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PciWrite32 (Address, 0xFFFFFFFF);
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*Value = PciRead32 (Address);
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PciWrite32 (Address, *OriginalValue);
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//
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// Enable interrupt
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//
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EnableInterrupts ();
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}
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STATIC
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VOID
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PcatPciRootBridgeParseBars (
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IN UINT16 Command,
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IN UINTN Bus,
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IN UINTN Device,
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IN UINTN Function,
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IN UINTN BarOffsetBase,
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IN UINTN BarOffsetEnd,
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IN PCI_ROOT_BRIDGE_APERTURE *Io,
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IN PCI_ROOT_BRIDGE_APERTURE *Mem,
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IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G,
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IN PCI_ROOT_BRIDGE_APERTURE *PMem,
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IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G
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)
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{
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UINT32 OriginalValue;
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UINT32 Value;
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UINT32 OriginalUpperValue;
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UINT32 UpperValue;
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UINT64 Mask;
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UINTN Offset;
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UINT64 Base;
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UINT64 Length;
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UINT64 Limit;
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PCI_ROOT_BRIDGE_APERTURE *MemAperture;
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for (Offset = BarOffsetBase; Offset < BarOffsetEnd; Offset += sizeof (UINT32)) {
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PcatPciRootBridgeBarExisted (
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PCI_LIB_ADDRESS (Bus, Device, Function, Offset),
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&OriginalValue, &Value
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);
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if (Value == 0) {
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continue;
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}
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if ((Value & BIT0) == BIT0) {
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//
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// IO Bar
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//
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if (Command & EFI_PCI_COMMAND_IO_SPACE) {
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Mask = 0xfffffffc;
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Base = OriginalValue & Mask;
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Length = ((~(Value & Mask)) & Mask) + 0x04;
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if (!(Value & 0xFFFF0000)) {
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Length &= 0x0000FFFF;
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}
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Limit = Base + Length - 1;
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if (Base < Limit) {
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if (Io->Base > Base) {
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Io->Base = Base;
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}
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if (Io->Limit < Limit) {
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Io->Limit = Limit;
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}
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}
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}
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} else {
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//
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// Mem Bar
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//
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if (Command & EFI_PCI_COMMAND_MEMORY_SPACE) {
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Mask = 0xfffffff0;
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Base = OriginalValue & Mask;
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Length = Value & Mask;
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if ((Value & (BIT1 | BIT2)) == 0) {
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//
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// 32bit
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//
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Length = ((~Length) + 1) & 0xffffffff;
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if ((Value & BIT3) == BIT3) {
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MemAperture = PMem;
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} else {
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MemAperture = Mem;
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}
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} else {
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//
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// 64bit
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//
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Offset += 4;
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PcatPciRootBridgeBarExisted (
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PCI_LIB_ADDRESS (Bus, Device, Function, Offset),
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&OriginalUpperValue,
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&UpperValue
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);
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Base = Base | LShiftU64 ((UINT64) OriginalUpperValue, 32);
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Length = Length | LShiftU64 ((UINT64) UpperValue, 32);
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Length = (~Length) + 1;
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if ((Value & BIT3) == BIT3) {
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MemAperture = PMemAbove4G;
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} else {
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MemAperture = MemAbove4G;
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}
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}
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Limit = Base + Length - 1;
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if (Base < Limit) {
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if (MemAperture->Base > Base) {
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MemAperture->Base = Base;
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}
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if (MemAperture->Limit < Limit) {
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MemAperture->Limit = Limit;
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}
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}
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}
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}
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}
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}
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PCI_ROOT_BRIDGE *
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ScanForRootBridges (
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UINTN *NumberOfRootBridges
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)
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{
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UINTN PrimaryBus;
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UINTN SubBus;
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UINT8 Device;
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UINT8 Function;
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UINTN NumberOfDevices;
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UINT64 Address;
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PCI_TYPE01 Pci;
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UINT64 Attributes;
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UINT64 Base;
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UINT64 Limit;
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UINT64 Value;
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PCI_ROOT_BRIDGE_APERTURE Io, Mem, MemAbove4G, PMem, PMemAbove4G, *MemAperture;
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PCI_ROOT_BRIDGE *RootBridges;
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UINTN BarOffsetEnd;
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*NumberOfRootBridges = 0;
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RootBridges = NULL;
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//
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// After scanning all the PCI devices on the PCI root bridge's primary bus,
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// update the Primary Bus Number for the next PCI root bridge to be this PCI
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// root bridge's subordinate bus number + 1.
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//
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for (PrimaryBus = 0; PrimaryBus <= PCI_MAX_BUS; PrimaryBus = SubBus + 1) {
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SubBus = PrimaryBus;
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Attributes = 0;
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Io.Base = Mem.Base = MemAbove4G.Base = PMem.Base = PMemAbove4G.Base = MAX_UINT64;
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Io.Limit = Mem.Limit = MemAbove4G.Limit = PMem.Limit = PMemAbove4G.Limit = 0;
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//
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// Scan all the PCI devices on the primary bus of the PCI root bridge
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//
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for (Device = 0, NumberOfDevices = 0; Device <= PCI_MAX_DEVICE; Device++) {
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for (Function = 0; Function <= PCI_MAX_FUNC; Function++) {
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//
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// Compute the PCI configuration address of the PCI device to probe
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//
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Address = PCI_LIB_ADDRESS (PrimaryBus, Device, Function, 0);
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//
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// Read the Vendor ID from the PCI Configuration Header
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//
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if (PciRead16 (Address) == MAX_UINT16) {
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if (Function == 0) {
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//
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// If the PCI Configuration Read fails, or a PCI device does not
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// exist, then skip this entire PCI device
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//
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break;
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} else {
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//
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// If PCI function != 0, VendorId == 0xFFFF, we continue to search
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// PCI function.
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//
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continue;
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}
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}
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//
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// Read the entire PCI Configuration Header
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//
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PciReadBuffer (Address, sizeof (Pci), &Pci);
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//
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// Increment the number of PCI device found on the primary bus of the
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// PCI root bridge
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//
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NumberOfDevices++;
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//
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// Look for devices with the VGA Palette Snoop enabled in the COMMAND
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// register of the PCI Config Header
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//
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if ((Pci.Hdr.Command & EFI_PCI_COMMAND_VGA_PALETTE_SNOOP) != 0) {
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Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;
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Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;
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}
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BarOffsetEnd = 0;
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//
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// PCI-PCI Bridge
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//
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if (IS_PCI_BRIDGE (&Pci)) {
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//
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// Get the Bus range that the PPB is decoding
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//
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if (Pci.Bridge.SubordinateBus > SubBus) {
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//
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// If the suborinate bus number of the PCI-PCI bridge is greater
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// than the PCI root bridge's current subordinate bus number,
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// then update the PCI root bridge's subordinate bus number
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//
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SubBus = Pci.Bridge.SubordinateBus;
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}
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//
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// Get the I/O range that the PPB is decoding
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//
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Value = Pci.Bridge.IoBase & 0x0f;
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Base = ((UINT32) Pci.Bridge.IoBase & 0xf0) << 8;
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Limit = (((UINT32) Pci.Bridge.IoLimit & 0xf0) << 8) | 0x0fff;
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if (Value == BIT0) {
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Base |= ((UINT32) Pci.Bridge.IoBaseUpper16 << 16);
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Limit |= ((UINT32) Pci.Bridge.IoLimitUpper16 << 16);
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}
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if (Base < Limit) {
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if (Io.Base > Base) {
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Io.Base = Base;
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}
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if (Io.Limit < Limit) {
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Io.Limit = Limit;
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}
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}
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//
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// Get the Memory range that the PPB is decoding
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//
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Base = ((UINT32) Pci.Bridge.MemoryBase & 0xfff0) << 16;
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Limit = (((UINT32) Pci.Bridge.MemoryLimit & 0xfff0) << 16) | 0xfffff;
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if (Base < Limit) {
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if (Mem.Base > Base) {
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Mem.Base = Base;
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}
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if (Mem.Limit < Limit) {
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Mem.Limit = Limit;
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}
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}
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//
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// Get the Prefetchable Memory range that the PPB is decoding
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//
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Value = Pci.Bridge.PrefetchableMemoryBase & 0x0f;
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Base = ((UINT32) Pci.Bridge.PrefetchableMemoryBase & 0xfff0) << 16;
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Limit = (((UINT32) Pci.Bridge.PrefetchableMemoryLimit & 0xfff0)
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<< 16) | 0xfffff;
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MemAperture = &PMem;
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if (Value == BIT0) {
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Base |= LShiftU64 (Pci.Bridge.PrefetchableBaseUpper32, 32);
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Limit |= LShiftU64 (Pci.Bridge.PrefetchableLimitUpper32, 32);
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MemAperture = &PMemAbove4G;
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}
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if (Base < Limit) {
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if (MemAperture->Base > Base) {
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MemAperture->Base = Base;
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}
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if (MemAperture->Limit < Limit) {
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MemAperture->Limit = Limit;
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}
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}
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|
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//
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// Look at the PPB Configuration for legacy decoding attributes
|
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//
|
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if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_ISA)
|
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== EFI_PCI_BRIDGE_CONTROL_ISA) {
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Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO;
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Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO_16;
|
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Attributes |= EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO;
|
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}
|
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if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_VGA)
|
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== EFI_PCI_BRIDGE_CONTROL_VGA) {
|
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Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;
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Attributes |= EFI_PCI_ATTRIBUTE_VGA_MEMORY;
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Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO;
|
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if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_VGA_16)
|
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!= 0) {
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Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;
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Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO_16;
|
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}
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}
|
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BarOffsetEnd = OFFSET_OF (PCI_TYPE01, Bridge.Bar[2]);
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} else {
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//
|
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// Parse the BARs of the PCI device to get what I/O Ranges, Memory
|
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// Ranges, and Prefetchable Memory Ranges the device is decoding
|
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//
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if ((Pci.Hdr.HeaderType & HEADER_LAYOUT_CODE) == HEADER_TYPE_DEVICE) {
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BarOffsetEnd = OFFSET_OF (PCI_TYPE00, Device.Bar[6]);
|
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}
|
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}
|
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|
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PcatPciRootBridgeParseBars (
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Pci.Hdr.Command,
|
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PrimaryBus,
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Device,
|
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Function,
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OFFSET_OF (PCI_TYPE00, Device.Bar),
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BarOffsetEnd,
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&Io,
|
||||
&Mem, &MemAbove4G,
|
||||
&PMem, &PMemAbove4G
|
||||
);
|
||||
|
||||
//
|
||||
// See if the PCI device is an IDE controller
|
||||
//
|
||||
if (IS_CLASS2 (&Pci, PCI_CLASS_MASS_STORAGE,
|
||||
PCI_CLASS_MASS_STORAGE_IDE)) {
|
||||
if (Pci.Hdr.ClassCode[0] & 0x80) {
|
||||
Attributes |= EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO;
|
||||
Attributes |= EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO;
|
||||
}
|
||||
if (Pci.Hdr.ClassCode[0] & 0x01) {
|
||||
Attributes |= EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO;
|
||||
}
|
||||
if (Pci.Hdr.ClassCode[0] & 0x04) {
|
||||
Attributes |= EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO;
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// See if the PCI device is a legacy VGA controller or
|
||||
// a standard VGA controller
|
||||
//
|
||||
if (IS_CLASS2 (&Pci, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA) ||
|
||||
IS_CLASS2 (&Pci, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA)
|
||||
) {
|
||||
Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;
|
||||
Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;
|
||||
Attributes |= EFI_PCI_ATTRIBUTE_VGA_MEMORY;
|
||||
Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO;
|
||||
Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO_16;
|
||||
}
|
||||
|
||||
//
|
||||
// See if the PCI Device is a PCI - ISA or PCI - EISA
|
||||
// or ISA_POSITIVIE_DECODE Bridge device
|
||||
//
|
||||
if (Pci.Hdr.ClassCode[2] == PCI_CLASS_BRIDGE) {
|
||||
if (Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA ||
|
||||
Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_EISA ||
|
||||
Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA_PDECODE) {
|
||||
Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO;
|
||||
Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO_16;
|
||||
Attributes |= EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO;
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// If this device is not a multi function device, then skip the rest
|
||||
// of this PCI device
|
||||
//
|
||||
if (Function == 0 && !IS_PCI_MULTI_FUNC (&Pci)) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// If at least one PCI device was found on the primary bus of this PCI
|
||||
// root bridge, then the PCI root bridge exists.
|
||||
//
|
||||
if (NumberOfDevices > 0) {
|
||||
RootBridges = ReallocatePool (
|
||||
(*NumberOfRootBridges) * sizeof (PCI_ROOT_BRIDGE),
|
||||
(*NumberOfRootBridges + 1) * sizeof (PCI_ROOT_BRIDGE),
|
||||
RootBridges
|
||||
);
|
||||
ASSERT (RootBridges != NULL);
|
||||
InitRootBridge (
|
||||
Attributes, Attributes, 0,
|
||||
(UINT8) PrimaryBus, (UINT8) SubBus,
|
||||
&Io, &Mem, &MemAbove4G, &PMem, &PMemAbove4G,
|
||||
&RootBridges[*NumberOfRootBridges]
|
||||
);
|
||||
RootBridges[*NumberOfRootBridges].ResourceAssigned = TRUE;
|
||||
//
|
||||
// Increment the index for the next PCI Root Bridge
|
||||
//
|
||||
(*NumberOfRootBridges)++;
|
||||
}
|
||||
}
|
||||
|
||||
return RootBridges;
|
||||
}
|
||||
Loading…
Reference in New Issue