mirror of https://github.com/acidanthera/audk.git
MdePkg/BaseLib: Add support for the XSETBV instruction
*v2: refine the coding format.
https://bugzilla.tianocore.org/show_bug.cgi?id=3284
This patch is to support XSETBV instruction so as to support
Extended Control Register(XCR) write.
Extended Control Register(XCR) read has already been supported
by below commit to support XGETBV instruction:
9b3ca509ab
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Ni Ray <ray.ni@intel.com>
Cc: Yao Jiewen <jiewen.yao@intel.com>
Signed-off-by: Jiaxin Wu <Jiaxin.wu@intel.com>
Signed-off-by: Zhang Hongbin1 <hongbin1.zhang@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
This commit is contained in:
parent
f95cdd316c
commit
4ac0296201
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@ -2,7 +2,7 @@
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Provides string functions, linked list functions, math functions, synchronization
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Provides string functions, linked list functions, math functions, synchronization
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functions, file path functions, and CPU architecture-specific functions.
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functions, file path functions, and CPU architecture-specific functions.
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Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>
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Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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Copyright (c) Microsoft Corporation.<BR>
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Copyright (c) Microsoft Corporation.<BR>
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Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
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Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
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@ -7438,6 +7438,29 @@ AsmXGetBv (
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IN UINT32 Index
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IN UINT32 Index
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);
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);
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/**
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Executes a XSETBV instruction to write a 64-bit value to a Extended Control
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Register(XCR), and returns the value.
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Writes the 64-bit value specified by Value to the XCR specified by Index. The
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64-bit value written to the XCR is returned. No parameter checking is
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performed on Index or Value, and some of these may cause CPU exceptions. The
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caller must either guarantee that Index and Value are valid, or the caller
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must establish proper exception handlers. This function is only available on
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IA-32 and x64.
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@param Index The 32-bit XCR index to write.
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@param Value The 64-bit value to write to the XCR.
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@return Value
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**/
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UINT64
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EFIAPI
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AsmXSetBv (
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IN UINT32 Index,
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IN UINT64 Value
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);
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/**
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/**
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Executes a VMGEXIT instruction (VMMCALL with a REP prefix)
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Executes a VMGEXIT instruction (VMMCALL with a REP prefix)
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@ -1,7 +1,7 @@
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## @file
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## @file
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# Base Library implementation.
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# Base Library implementation.
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#
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#
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# Copyright (c) 2007 - 2020, Intel Corporation. All rights reserved.<BR>
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# Copyright (c) 2007 - 2021, Intel Corporation. All rights reserved.<BR>
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# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
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# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
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# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
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# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
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@ -184,6 +184,7 @@
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Ia32/DisableCache.nasm| GCC
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Ia32/DisableCache.nasm| GCC
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Ia32/RdRand.nasm
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Ia32/RdRand.nasm
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Ia32/XGetBv.nasm
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Ia32/XGetBv.nasm
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Ia32/XSetBv.nasm
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Ia32/VmgExit.nasm
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Ia32/VmgExit.nasm
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Ia32/DivS64x64Remainder.c
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Ia32/DivS64x64Remainder.c
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@ -318,6 +319,7 @@
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X64/DisablePaging64.nasm
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X64/DisablePaging64.nasm
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X64/RdRand.nasm
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X64/RdRand.nasm
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X64/XGetBv.nasm
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X64/XGetBv.nasm
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X64/XSetBv.nasm
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X64/VmgExit.nasm
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X64/VmgExit.nasm
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ChkStkGcc.c | GCC
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ChkStkGcc.c | GCC
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@ -0,0 +1,34 @@
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;------------------------------------------------------------------------------
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;
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; Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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; Module Name:
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;
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; XSetBv.nasm
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;
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; Abstract:
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;
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; AsmXSetBv function
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;
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; Notes:
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;
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;------------------------------------------------------------------------------
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SECTION .text
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;------------------------------------------------------------------------------
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; UINT64
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; EFIAPI
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; AsmXSetBv (
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; IN UINT32 Index,
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; IN UINT64 Value
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; );
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;------------------------------------------------------------------------------
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global ASM_PFX(AsmXSetBv)
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ASM_PFX(AsmXSetBv):
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mov edx, [esp + 12]
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mov eax, [esp + 8]
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mov ecx, [esp + 4]
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xsetbv
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ret
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@ -0,0 +1,34 @@
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;------------------------------------------------------------------------------
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;
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; Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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; SPDX-License-Identifier: BSD-2-Clause-Patent
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;
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; Module Name:
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;
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; XSetBv.nasm
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;
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; Abstract:
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;
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; AsmXSetBv function
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;
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; Notes:
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;
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;------------------------------------------------------------------------------
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DEFAULT REL
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SECTION .text
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;------------------------------------------------------------------------------
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; UINT64
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; EFIAPI
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; AsmXSetBv (
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; IN UINT32 Index,
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; IN UINT64 Value
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; );
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;------------------------------------------------------------------------------
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global ASM_PFX(AsmXSetBv)
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ASM_PFX(AsmXSetBv):
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mov rax, rdx ; meanwhile, rax <- return value
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shr rdx, 0x20 ; edx:eax contains the value to write
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xsetbv
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ret
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