mirror of https://github.com/acidanthera/audk.git
UefiPayloadPkg: Fix the issue detected by Uncrustify
Signed-off-by: Guo Dong <guo.dong@intel.com>
This commit is contained in:
Guo Dong
mergify[bot]
parent
c5811ef1b3
commit
4af5849556
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@ -42,23 +42,23 @@ typedef enum {
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DoNothing
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} FDT_NODE_TYPE;
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#define MEMORY_ATTRIBUTE_DEFAULT (EFI_RESOURCE_ATTRIBUTE_PRESENT | \
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EFI_RESOURCE_ATTRIBUTE_INITIALIZED | \
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EFI_RESOURCE_ATTRIBUTE_TESTED | \
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EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | \
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EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | \
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EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | \
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EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE )
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#define MEMORY_ATTRIBUTE_DEFAULT (EFI_RESOURCE_ATTRIBUTE_PRESENT | \
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EFI_RESOURCE_ATTRIBUTE_INITIALIZED | \
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EFI_RESOURCE_ATTRIBUTE_TESTED | \
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EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | \
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EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | \
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EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | \
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EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE)
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#define ROOT_BRIDGE_SUPPORTS_DEFAULT (EFI_PCI_IO_ATTRIBUTE_VGA_IO_16 | \
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EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16 | \
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EFI_PCI_IO_ATTRIBUTE_ISA_IO_16 | \
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EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO | \
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EFI_PCI_IO_ATTRIBUTE_VGA_IO | \
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EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY | \
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EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO | \
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EFI_PCI_IO_ATTRIBUTE_ISA_IO | \
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EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO )
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EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16 | \
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EFI_PCI_IO_ATTRIBUTE_ISA_IO_16 | \
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EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO | \
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EFI_PCI_IO_ATTRIBUTE_VGA_IO | \
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EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY | \
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EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO | \
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EFI_PCI_IO_ATTRIBUTE_ISA_IO | \
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EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO)
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extern VOID *mHobList;
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UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES *mPciRootBridgeInfo = NULL;
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@ -69,7 +69,7 @@ UPL_PCI_SEGMENT_INFO_HOB *mUplPciSegmentInfoHob;
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/**
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Build a Handoff Information Table HOB
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This function initialize a HOB region from EfiMemoryBegin to
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This function initializes a HOB region from EfiMemoryBegin to
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EfiMemoryTop. And EfiFreeMemoryBottom and EfiFreeMemoryTop should
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be inside the HOB region.
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@ -93,7 +93,7 @@ HobConstructor (
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/**
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It will record the memory node initialized.
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@param[in] Node memory node is going to parsing..
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@param[in] Node memory node is going to parsing.
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**/
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VOID
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RecordMemoryNode (
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@ -108,10 +108,10 @@ RecordMemoryNode (
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/**
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Check the memory node if initialized.
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@param[in] Node memory node is going to parsing..
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@param[in] Node memory node is going to parsing.
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@return TRUE memory node was initialized. don't parse it again.
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@return FALSE memory node wasn't initialized , go to parse it.
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@return FALSE memory node wasn't initialized, go to parse it.
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**/
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BOOLEAN
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CheckMemoryNodeIfInit (
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@ -133,7 +133,7 @@ CheckMemoryNodeIfInit (
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It will check device node from FDT.
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@param[in] NodeString Device node name string.
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@param[in] Depth Check layer of Device node , only parse the 1st layer
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@param[in] Depth Check layer of Device node, only parse the 1st layer
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@return FDT_NODE_TYPE what type of the device node.
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**/
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@ -144,15 +144,15 @@ CheckNodeType (
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)
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{
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DEBUG ((DEBUG_INFO, "\n CheckNodeType %a \n", NodeString));
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if (AsciiStrnCmp (NodeString, "serial@", AsciiStrLen ("serial@")) == 0 ) {
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if (AsciiStrnCmp (NodeString, "serial@", AsciiStrLen ("serial@")) == 0) {
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return SerialPort;
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} else if (AsciiStrnCmp (NodeString, "reserved-memory", AsciiStrLen ("reserved-memory")) == 0 ) {
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} else if (AsciiStrnCmp (NodeString, "reserved-memory", AsciiStrLen ("reserved-memory")) == 0) {
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return ReservedMemory;
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} else if (AsciiStrnCmp (NodeString, "memory@", AsciiStrLen ("memory@")) == 0 ) {
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} else if (AsciiStrnCmp (NodeString, "memory@", AsciiStrLen ("memory@")) == 0) {
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return Memory;
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} else if (AsciiStrnCmp (NodeString, "framebuffer@", AsciiStrLen ("framebuffer@")) == 0) {
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return FrameBuffer;
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} else if (AsciiStrnCmp (NodeString, "pci-rb", AsciiStrLen ("pci-rb")) == 0 ) {
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} else if (AsciiStrnCmp (NodeString, "pci-rb", AsciiStrLen ("pci-rb")) == 0) {
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return PciRootBridge;
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} else if (AsciiStrCmp (NodeString, "options") == 0) {
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return Options;
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@ -571,9 +571,9 @@ ParsegraphicNode (
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**/
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VOID
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ParseSerialPort (
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IN VOID *Fdt,
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IN INT32 SubNode,
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IN UINT32 AddressCells
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IN VOID *Fdt,
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IN INT32 SubNode,
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IN UINT32 AddressCells
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)
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{
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UNIVERSAL_PAYLOAD_SERIAL_PORT_INFO *Serial;
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@ -599,14 +599,14 @@ ParseSerialPort (
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PropertyPtr = FdtGetProperty (Fdt, SubNode, "current-speed", &TempLen);
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ASSERT (TempLen > 0);
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if (TempLen > 0) {
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Data32 = (UINT32 *)(PropertyPtr->Data);
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Data32 = (UINT32 *)(PropertyPtr->Data);
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Serial->BaudRate = Fdt32ToCpu (*Data32);
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}
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PropertyPtr = FdtGetProperty (Fdt, SubNode, "reg-shift", &TempLen);
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if (TempLen > 0) {
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Data32 = (UINT32 *)(PropertyPtr->Data);
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Serial->RegisterStride = (UINT8) (1 << Fdt32ToCpu (*Data32));
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Data32 = (UINT32 *)(PropertyPtr->Data);
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Serial->RegisterStride = (UINT8)(1 << Fdt32ToCpu (*Data32));
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}
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PropertyPtr = FdtGetProperty (Fdt, SubNode, "reg", &TempLen);
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@ -620,6 +620,7 @@ ParseSerialPort (
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if (Value32 < SIZE_64KB) {
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Serial->UseMmio = FALSE;
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}
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break;
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case 2:
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Serial->RegisterBase = Fdt32ToCpu (Data32[1]);
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@ -629,12 +630,14 @@ ParseSerialPort (
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} else {
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Serial->RegisterBase |= LShiftU64 (Value32, 32);
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}
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break;
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case 3:
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// First U32 format: npt000ss bbbbbbbb dddddfff rrrrrrrr
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if ((Value32 & 0x03000000) == 0x01000000) {
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Serial->UseMmio = FALSE;
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}
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Serial->RegisterBase = LShiftU64 ((UINT64)Fdt32ToCpu (Data32[1]), 32) | Fdt32ToCpu (Data32[2]);
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break;
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default:
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@ -642,6 +645,7 @@ ParseSerialPort (
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break;
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}
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}
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DEBUG ((DEBUG_INFO, "Serial->UseMmio = %x\n", Serial->UseMmio));
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DEBUG ((DEBUG_INFO, "Serial->RegisterBase = 0x%x\n", Serial->RegisterBase));
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DEBUG ((DEBUG_INFO, "Serial->BaudRate = %d\n", Serial->BaudRate));
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@ -716,7 +720,7 @@ ParsePciRootBridge (
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}
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AddressCells = 3;
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PropertyPtr = FdtGetProperty (Fdt, Node, "#address-cells", &TempLen);
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PropertyPtr = FdtGetProperty (Fdt, Node, "#address-cells", &TempLen);
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if ((PropertyPtr != NULL) && (TempLen > 0)) {
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AddressCells = Fdt32ToCpu (*(UINT32 *)PropertyPtr->Data);
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}
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@ -750,7 +754,7 @@ ParsePciRootBridge (
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TempStr = FdtGetString (Fdt, Fdt32ToCpu (PropertyPtr->NameOffset), NULL);
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if (AsciiStrCmp (TempStr, "ranges") == 0) {
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DEBUG ((DEBUG_INFO, " Found ranges Property TempLen (%08X), limit %x\n", TempLen, TempLen/sizeof (UINT32)));
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DEBUG ((DEBUG_INFO, " Found ranges Property TempLen (%08X), limit %x\n", TempLen, TempLen / sizeof (UINT32)));
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mPciRootBridgeInfo->RootBridge[RbIndex].AllocationAttributes = EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | EFI_PCI_HOST_BRIDGE_MEM64_DECODE;
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mPciRootBridgeInfo->RootBridge[RbIndex].Supports = ROOT_BRIDGE_SUPPORTS_DEFAULT;
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@ -762,18 +766,18 @@ ParsePciRootBridge (
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mPciRootBridgeInfo->RootBridge[RbIndex].HID = EISA_PNP_ID (0x0A03);
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Data32 = (UINT32 *)(PropertyPtr->Data);
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for (Base = 0; Base < TempLen/sizeof (UINT32); Base = Base + DWORDS_TO_NEXT_ADDR_TYPE) {
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for (Base = 0; Base < TempLen / sizeof (UINT32); Base = Base + DWORDS_TO_NEXT_ADDR_TYPE) {
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DEBUG ((DEBUG_INFO, " Base :%x \n", Base));
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MemType = Fdt32ToCpu (*(Data32 + Base));
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if (((MemType) & (SS_64BIT_MEMORY_SPACE)) == SS_64BIT_MEMORY_SPACE) {
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mPciRootBridgeInfo->RootBridge[RbIndex].MemAbove4G.Base = Fdt32ToCpu (*(Data32 + Base + 2)) + LShiftU64 (Fdt32ToCpu (*(Data32 + Base + 1)), 32);
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mPciRootBridgeInfo->RootBridge[RbIndex].MemAbove4G.Limit = mPciRootBridgeInfo->RootBridge[RbIndex].MemAbove4G.Base + LShiftU64 (Fdt32ToCpu (*(Data32 + Base + 5)), 32) + Fdt32ToCpu (*(Data32 + Base + 6)) -1;
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mPciRootBridgeInfo->RootBridge[RbIndex].MemAbove4G.Limit = mPciRootBridgeInfo->RootBridge[RbIndex].MemAbove4G.Base + LShiftU64 (Fdt32ToCpu (*(Data32 + Base + 5)), 32) + Fdt32ToCpu (*(Data32 + Base + 6)) - 1;
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} else if (((MemType) & (SS_32BIT_MEMORY_SPACE)) == SS_32BIT_MEMORY_SPACE) {
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mPciRootBridgeInfo->RootBridge[RbIndex].Mem.Base = Fdt32ToCpu (*(Data32 + Base + 2));
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mPciRootBridgeInfo->RootBridge[RbIndex].Mem.Limit = mPciRootBridgeInfo->RootBridge[RbIndex].Mem.Base + Fdt32ToCpu (*(Data32 + Base + 6)) -1;
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mPciRootBridgeInfo->RootBridge[RbIndex].Mem.Limit = mPciRootBridgeInfo->RootBridge[RbIndex].Mem.Base + Fdt32ToCpu (*(Data32 + Base + 6)) - 1;
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} else if (((MemType) & (SS_IO_SPACE)) == SS_IO_SPACE) {
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mPciRootBridgeInfo->RootBridge[RbIndex].Io.Base = Fdt32ToCpu (*(Data32 + Base + 2));
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mPciRootBridgeInfo->RootBridge[RbIndex].Io.Limit = mPciRootBridgeInfo->RootBridge[RbIndex].Io.Base + Fdt32ToCpu (*(Data32 + Base + 6)) -1;
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mPciRootBridgeInfo->RootBridge[RbIndex].Io.Limit = mPciRootBridgeInfo->RootBridge[RbIndex].Io.Base + Fdt32ToCpu (*(Data32 + Base + 6)) - 1;
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}
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}
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@ -869,9 +873,9 @@ ParseDtb (
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index = 0;
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// TODO: This value comes from FDT. Currently there is a bug in implementation
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// which assumes node ordering. Which requires a fix.
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PciEnumDone = 1;
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BootMode = 0;
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NodeType = 0;
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PciEnumDone = 1;
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BootMode = 0;
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NodeType = 0;
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RootAddressCells = 2;
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DEBUG ((DEBUG_INFO, "FDT = 0x%x %x\n", Fdt, Fdt32ToCpu (*((UINT32 *)Fdt))));
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@ -909,7 +913,7 @@ ParseDtb (
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DEBUG ((DEBUG_INFO, "FreeMemoryBottom :0x%llx\n", FreeMemoryBottom));
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DEBUG ((DEBUG_INFO, "FreeMemoryTop :0x%llx\n", FreeMemoryTop));
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DEBUG ((DEBUG_INFO, "MemoryTop :0x%llx\n", MemoryTop));
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mHobList = HobConstructor ((VOID *)(UINTN)MemoryBottom, (VOID *)(UINTN)MemoryTop, (VOID *)(UINTN)FreeMemoryBottom, (VOID *)(UINTN)FreeMemoryTop);
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mHobList = HobConstructor ((VOID *)(UINTN)MemoryBottom, (VOID *)(UINTN)MemoryTop, (VOID *)(UINTN)FreeMemoryBottom, (VOID *)(UINTN)FreeMemoryTop);
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IsHobConstructed = TRUE;
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NewHobList = (UINTN)mHobList;
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break;
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@ -917,8 +921,7 @@ ParseDtb (
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}
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}
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}
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} // end of memory node
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else {
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} else {
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PropertyPtr = FdtGetProperty (Fdt, Node, "compatible", &TempLen);
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if (PropertyPtr == NULL) {
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continue;
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@ -1037,9 +1040,10 @@ ParseDtb (
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/**
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It will Parse FDT -node based on information from bootloaders.
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@param[in] FdtBase The starting memory address of FdtBase
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@retval HobList The base address of Hoblist.
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@param[in] FdtBase The starting memory address of FdtBase
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@retval HobList The base address of Hoblist.
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**/
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UINTN
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EFIAPI
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@ -1068,7 +1072,7 @@ UplInitHob (
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NHobAddress = 0;
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//
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// Check parameter type(
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// Check parameter type
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//
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if (FdtCheckHeader (FdtBase) == 0) {
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DEBUG ((DEBUG_INFO, "%a() FDT blob\n", __func__));
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