mirror of https://github.com/acidanthera/audk.git
OvmfPkg/PlatformPei: Merge Xen support into MemMapInitialization
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Wei Liu <wei.liu2@citrix.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15205 6f19259b-4bc3-4df7-8a09-765794883524
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@ -1,7 +1,7 @@
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/**@file
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Memory Detection for Virtual Machines.
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Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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@ -35,9 +35,9 @@ Module Name:
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#include "Platform.h"
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#include "Cmos.h"
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STATIC
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UINTN
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UINT32
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GetSystemMemorySizeBelow4gb (
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VOID
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)
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{
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UINT8 Cmos0x34;
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@ -164,7 +164,7 @@ AddUntestedMemoryRangeHob (
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}
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VOID
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XenMemMapInitialization (
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MemMapInitialization (
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VOID
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)
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{
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@ -193,55 +193,29 @@ XenMemMapInitialization (
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//
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AddIoMemoryRangeHob (0x0A0000, BASE_1MB);
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XenPublishRamRegions ();
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}
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if (!mXen) {
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UINT32 TopOfLowRam;
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TopOfLowRam = GetSystemMemorySizeBelow4gb ();
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VOID
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MemMapInitialization (
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EFI_PHYSICAL_ADDRESS TopOfMemory
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)
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{
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//
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// Create Memory Type Information HOB
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//
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BuildGuidDataHob (
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&gEfiMemoryTypeInformationGuid,
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mDefaultMemoryTypeInformation,
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sizeof(mDefaultMemoryTypeInformation)
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);
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//
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// Add PCI IO Port space available for PCI resource allocations.
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//
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BuildResourceDescriptorHob (
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EFI_RESOURCE_IO,
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EFI_RESOURCE_ATTRIBUTE_PRESENT |
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EFI_RESOURCE_ATTRIBUTE_INITIALIZED,
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0xC000,
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0x4000
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);
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//
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// Video memory + Legacy BIOS region
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//
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AddIoMemoryRangeHob (0x0A0000, BASE_1MB);
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//
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// address purpose size
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// ------------ -------- -------------------------
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// max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)
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// 0xFC000000 gap 44 MB
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// 0xFEC00000 IO-APIC 4 KB
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// 0xFEC01000 gap 1020 KB
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// 0xFED00000 HPET 1 KB
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// 0xFED00400 gap 1023 KB
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// 0xFEE00000 LAPIC 1 MB
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//
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AddIoMemoryRangeHob (TopOfMemory < BASE_2GB ? BASE_2GB : TopOfMemory, 0xFC000000);
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AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);
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AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);
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AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);
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//
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// address purpose size
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// ------------ -------- -------------------------
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// max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)
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// 0xFC000000 gap 44 MB
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// 0xFEC00000 IO-APIC 4 KB
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// 0xFEC01000 gap 1020 KB
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// 0xFED00000 HPET 1 KB
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// 0xFED00400 gap 1023 KB
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// 0xFEE00000 LAPIC 1 MB
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//
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AddIoMemoryRangeHob (TopOfLowRam < BASE_2GB ?
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BASE_2GB : TopOfLowRam, 0xFC000000);
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AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);
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AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);
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AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);
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} else {
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XenPublishRamRegions ();
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}
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}
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@ -370,10 +344,6 @@ InitializePlatform (
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IN CONST EFI_PEI_SERVICES **PeiServices
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)
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{
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EFI_PHYSICAL_ADDRESS TopOfMemory;
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TopOfMemory = 0;
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DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));
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DebugDumpCmos ();
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@ -385,7 +355,7 @@ InitializePlatform (
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PublishPeiMemory ();
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if (!mXen) {
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TopOfMemory = MemDetect ();
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MemDetect ();
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}
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if (mXen) {
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@ -397,11 +367,7 @@ InitializePlatform (
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PeiFvInitialization ();
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if (mXen) {
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XenMemMapInitialization ();
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} else {
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MemMapInitialization (TopOfMemory);
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}
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MemMapInitialization ();
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MiscInitialization ();
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@ -64,6 +64,11 @@ PublishPeiMemory (
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VOID
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);
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UINT32
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GetSystemMemorySizeBelow4gb (
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VOID
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);
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EFI_PHYSICAL_ADDRESS
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MemDetect (
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VOID
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